A circuit board includes a first wiring layer and a build-up structure. The build-up structure includes at least one dielectric layer and at least one second wiring layer. Each dielectric layer and each second wiring layer are alternately arranged. The at least one dielectric layer comprises an outermost dielectric layer. The at least one second wiring layer is formed on a side of the outermost dielectric layer, and comprises an outermost second wiring layer. A portion of the first wiring layer is embedded in a side of the outermost dielectric layer facing away the outermost second wiring layer, a remaining portion of the first wiring layer protrudes from the outermost dielectric layer. A method for manufacturing a circuit board is provided.

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

The present disclosure relates to a printed circuit board including a first insulating layer including a non-photosensitive insulating material, a first wiring layer embedded in the first insulating layer, where an upper surface thereof is exposed from the upper surface of the first insulating layer, includes a first metal layer, and a second metal layer covering at least a portion of each of the lower surface and side surface of the first metal layer with a thickness thinner than the first metal layer, and a second insulating layer disposed under the lower surface of the first insulating layer to cover at least a portion of a lower surface of the first wiring layer, and including the non-photosensitive insulating material.

A method for manufacturing a package substrate including an insulating layer and a wiring conductor, including: forming, on one or both sides of a core resin layer, a substrate including a peelable first metal layer that has a thickness of 1-70 ?m, a first insulating resin layer, and a second metal layer; forming a non-through hole reaching a surface of the first metal layer, performing electrolytic and/or electroless copper plating on its inner wall, and connecting the second and first metal layers; arranging a second insulating resin layer and a third metal layer and heating and pressurizing the first substrate to form a substrate; forming a non-through hole reaching a surface of the second metal layer, performing electrolytic and/or electroless copper plating on its inner wall, and connecting the second and third metal layers; peeling a third substrate; and patterning the first and third metal layers to form the wiring conductor.

A printed circuit board comprises an epoxy-containing member, a first copper pattern disposed adjacent to the epoxy-containing member, and a first adhesion promoter layer interposed between the epoxy-containing member and the first copper pattern.

A method for manufacturing a package substrate for mounting a semiconductor device including: a first laminate preparing step of preparing a first laminate including a resin layer, a bonding layer that is provided on at least one surface side of the resin layer and includes peeling means, and a first metal layer provided on the bonding layer; a first wiring forming step of forming a first wiring conductor in the first laminate by etching the first metal layer; a second laminate forming step of forming a second laminate by laminating an insulating resin layer and a second metal layer in this order on a surface of the first laminate, the surface being provided with the first wiring conductor; a second wiring forming step of forming a second wiring conductor on the insulating resin layer by forming a non-through hole in the insulating resin layer.

A circuit board and a method of manufacturing a circuit board or two circuit boards are illustrated and described. The circuit board includes (a) a dielectric layer with a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis perpendicular thereto and a layer thickness along a z-direction which is perpendicular with respect to the x-axis and to the y-axis; (b) a metallic layer which is attached to the dielectric layer in a planar manner; and (c) a component which is embedded in the dielectric layer and/or in a dielectric core-layer of the circuit board. The dielectric layer includes a dielectric material which has (i) an elastic modulus E in a range between 1 and 20 GPa and (ii) a coefficient of thermal expansion in a range between 0 and 17 ppm/K along the x-axis and along the y-axis.

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

A method for manufacturing an electronic component by a pressure-assisted low-temperature sintering process, by using a pressure sintering device having an upper die and a lower die is disclosed. The upper the die and/or the lower die is provided with a first pressure pad, wherein the method includes the following steps: placing a first sinterable component on a first sintering layer provided on a top layer of a first substrate; joining the sinterable component and the top layer of the first substrate to form a first electronic component by pressing the upper die and the lower die towards each other, wherein the sintering device is simultaneously heated.

An embedded board includes an insulating layer and an electronic device embedded in the insulating layer. A first circuit pattern is embedded to contact a bottom surface of the insulating layer, and a second circuit pattern protrudes from the bottom surface of the insulating layer. A via is bonded to the device and the second circuit pattern.