A printed circuit board comprises a first mounting surface, a second mounting surface, and a piezoelectric transformer. The piezoelectric transformer has a piezoelectric substance, external electrodes, and a frame substrate. The second mounting surface has a projection region. There is a first region from a first location, where an end portion further from the output electrode out of end portions of the input electrode is projected onto the second mounting surface in the projection region, to a second location, where an end portion closer to the output electrode out of the end portions of the input electrode is projected onto the second mounting surface, the first region being a mounting allowed region where an electronic component is mounted.

A curved electronic device (10c) can be formed by a stack with a curved substrate (13) comprising a thermoplastic material (Ms), and at least one electronic component (14) connected to an electronic circuit (15) disposed on the substrate (13). A component area (11) of the substrate surface (11.12) around the electronic component (14) comprises a first material (M1) providing relatively low absorption (A1) to light (L) and a surrounding area (12) of the substrate (13) outside the component area (11), comprises a second material (M2) providing relatively high absorption (A2) of the light (L). E.g. as a result of differential heating and thermoforming a first thickness (T1) of the substrate (13) in the component area (11) may be relatively high compared to a second thickness (T2) of the substrate (13) in the surrounding area (12).

A planar coil element of the present invention includes an insulating base film having a first surface and a second surface opposite to the first surface, a first conductive pattern deposited on the first surface side of the insulating base film, and a first insulating layer covering the first conductive pattern on the first surface side, in which the first conductive pattern includes a core body and a widening layer deposited by plating on the outer surface of the core body, the core body includes a thin conductive layer on the insulating base film, and the ratio of the average thickness of the first conductive pattern to the average circuit pitch of the first conductive pattern is 1/2 or more and 5 or less.

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

A component carrier includes an electrically insulating layer structure with a first main surface and a second main surface, a through hole extends through the electrically insulating layer structure between the first main surface and the second main surface. The through hole has a first tapering portion extending from the first main surface and a second tapering portion extending from the second main surface. The through hole is delimited by a first plating structure on at least part of the sidewalls of the electrically insulating layer structure and a second plating structure formed separately from and arranged on the first plating structure. The second plating structure includes an electrically conductive bridge structure connecting the opposing sidewalls.

A method of copper electroplating in the manufacture of printed circuit boards. The method is used for filling through-holes and micro-vias with copper. The method includes the steps of: (1) preparing an electronic substrate to receive copper electroplating thereon; (2) forming at least one of one or more through-holes and/or one or more micro-vias in the electronic substrate; and (3) electroplating copper in the at one or more through-holes and/or one or more micro-vias by contacting the electronic substrate with an acid copper electroplating solution. The acid copper plating solution comprises a source of copper ions; sulfuric acid; a source of chloride ions; a brightener; a wetter; and a leveler. The acid copper electroplating solution plates the one or more through-holes and/or the one or more micro-vias until metallization is complete.

A method for closing a channel-shaped opening with a cross-sectional area and a passage length, more particularly through-bores or plated through-holes in printed circuit boards, using a liquid curable or curing filler material. The opening is closed by a digitally controlled application method with two discharge heads arranged opposite one another, preferably in an inkjet method with two discharge heads designed as print heads and arranged opposite one another. The two discharge heads are controlled such that the opening is filled with the filler material from both sides through the two ends simultaneously. The filler material is discharged by the two discharge heads such that the quantities of discharged filler material meet inside the opening.

A lighting module of a motor vehicle signaling device includes a ceramic substrate having opposite first and second faces, and a plurality of selectively activatable light sources mounted on the first face of the ceramic substrate. Each of the first and second faces of the ceramic substrate are provided with at least a first and a second respective interconnection layer. The ceramic substrate comprises a plurality of through holes designed to interconnect the first interconnection layer to the second interconnection layer.

An electrical connector mountable to a substrate (e.g. a Printed Circuit Board, PCB) can include a terminal housing having a front wall and an opposing back wall. An opening is provided in the front wall for receiving a plug inside the terminal housing, opposing side walls, and a top wall and an opposing bottom wall. The bottom wall has an inner surface facing the inside of the terminal housing and an outer surface facing away from the inside of the terminal housing. The outer surface (can have at least two retention pins projecting from the outer surface for being inserted into corresponding holes in the PCB. A first retention pin can be positioned on the outer surface so as to be arranged asymmetrically with respect to a second retention pin.

A multilayer body includes insulator layers including a first insulator layer laminated in a vertical direction. Electrodes include a signal electrode and are provided at an upper main surface of the first insulator layer and arranged in a transverse direction. At least a portion of each of the electrodes is exposed to outside from a circuit board. First and second interlayer connection conductors extend through the first insulator layer in the vertical direction and electrically connect the signal electrode and a signal conductor layer. Mounting portions are located at the portions of the electrodes that are exposed to the outside from the circuit board. The first and second interlayer connection conductors are electrically connected to the signal electrode so as not to overlap the mounting portion that is provided at the signal electrode.