The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

A memory device includes a first SRAM cell, a second SRAM cell, a first inter transistor and a second inter transistor. The first SRAM cell includes two first pull-up transistors, two first pull-down transistors, and two first pass-gate transistors. The second SRAM cell includes two second pull-up transistors, two second pull-down transistors, and two second pass-gate transistors. The first inter transistor and the second inter transistor are electrically connected to the first SRAM cell and the second SRAM cell.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.

Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the six transistors is being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors. The at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate. A first inverter is formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter is formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in the third deck.

A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.

An integrated circuit (IC) that includes a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region. Each of the first and the second p-type active regions includes a first group of vertically stacked channel layers having a width W1, and each of the first and the second n-type active regions includes a second group of vertically stacked channel layers having a width W2, where W2 is less than W1. The IC structure further includes a standard logic cell having a third n-type fin and a third p-type fin. The third n-type fin includes a third group of vertically stacked channel layers having a width W3, and the third p-type fin includes a fourth group of vertically stacked channel layers having a width W4, where W3 is greater than or equal to W4.

A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

A method for forming a first impurity region 3 connected to lower portions of first semiconductor pillars and second impurity regions 4a and 4b connected to lower portions of second semiconductor pillars includes forming a semiconductor layer 100 having an impurity concentration lower than an impurity concentration of each of the first impurity region 3 and the second impurity regions 4a and 4b in impurity boundary regions of the first impurity region 3 and the second impurity regions 4a and 4b in a vertical direction and a horizontal direction.