Disclosed herein is an apparatus that includes a semiconductor substrate having source/drain regions and a gate trench located between the source/drain regions; and a gate electrode embedded in the gate trench via a gate insulating film. The gate electrode includes a first polycrystalline silicon film located at a bottom of the gate trench and a metal film stacked on the first polycrystalline silicon film. The first polycrystalline silicon film is doped with boron.

The present application provides a method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a substrate; forming a first conductive material layer on the substrate; performing plasma treatment on the first conductive material layer to form a first conductive layer; successively forming a second conductive layer, a first block layer, a third conductive layer and a fourth conductive layer on the first conductive layer; forming a dielectric layer on the fourth conductive layer, and forming an ohmic contact layer at a junction of the first conductive layer and the second conductive layer; forming an initial bit line structure; performing NH.sub.3/N.sub.2 plasma treatment on the initial bit line structure to form a second block layer on a sidewall of the first conductive layer and a third block layer on a sidewall of the ohmic contact layer.

A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a metal oxide and a first conductor that is electrically connected to the metal oxide. The capacitor includes a first insulator which is provided over the metal oxide and which the first conductor penetrates; a second insulator provided over the first insulator and including an opening reaching the first insulator and the first conductor; a second conductor in contact with an inner wall of the opening, the first insulator, and the first conductor; a third insulator provided over the second conductor; and a fourth conductor provided over the third insulator. The first insulator has higher capability of inhibiting the passage of hydrogen than the second insulator.

A method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line. Other embodiments, including structure independent of method, are disclosed.

The present disclosure provides a method for preparing a semiconductor device. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate. The method also includes depositing a dielectric layer over the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug. A first portion of the dielectric layer extends between the first metal plug and the second metal plug such that the first portion of the dielectric layer and the semiconductor substrate are separated by an airgap while a second portion of the dielectric layer extends between the third metal plug and the fourth metal plug such that the second portion of the dielectric layer is in direct contact with the semiconductor substrate.

A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region. having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

A semiconductor integrated circuit device may include a semiconductor chip, a power line region and a reservoir capacitor. The semiconductor chip may include a cell region and a peripheral circuit region. The power line region may be arranged on an edge portion of the peripheral circuit region. The reservoir capacitor may be formed on the power line region.