Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

A memory includes a plurality of semiconductor structures stacked onto one another. Each of the plurality of semiconductor structures include: a first base including a peripheral circuit structure; a first integrated circuit layer disposed on the first base and electrically connected to the peripheral circuit structure; and a second base disposed on the first integrated circuit layer. A first dielectric layer is disposed between the first integrated circuit layer and the second base. The second base includes a storage circuit structure. Each of the first base and the second base includes a semiconductor layer.

A method of forming semiconductor device, including forming a first protective strip and a second protective strip on a semiconductor substrate. The first protective strip and the second protective strip extend in a first direction and are alternately arranged in a second direction perpendicular to the first direction. The first protective strip and the second protective strip are spaced apart from each other. The first protective strip is cut by selectively removing a portion of the first protective strip. The second protective strip is cut by selectively removing a portion of the second protective strip. The semiconductor substrate is etched to form an isolation trench. Remaining portions of the first and second protective strips are removed. An isolation feature is filled into the isolation trench. The isolation feature defines a plurality of strip-shaped active regions. Capacitor contacts are formed on both ends of each of the strip-shaped active regions.

Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.

Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A method used in forming an array of vertical transistors comprises forming laterally-spaced vertical projections that project upwardly from a substrate in a vertical cross-section. The vertical projections individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. First gate insulator material is formed along opposing sidewalls of the channel region in the vertical cross-section. One of (a) or (b) is formed over opposing sidewalls of the first gate insulator material in the vertical cross-section, where (a): conductive gate lines that are horizontally elongated through the vertical cross-section; and (b): sacrificial placeholder gate lines that are horizontally elongated through the vertical cross-section. The one of the (a) or the (b) laterally overlaps the upper source/drain region and the lower source/drain region. The first gate insulator material has a top that is below a top of the channel region and has a bottom that is above a bottom of the channel region. An upper void space is laterally between the one of the (a) or the (b) and both of the upper source/drain region and the channel region. A lower void space is laterally between the one of the (a) or the (b) and both of the lower source/drain region and the channel region. Second gate insulator material is formed in the upper and lower void spaces. Other embodiments, including structure independent of method, are disclosed.

A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry at least partially overlying the first semiconductive structure, first back-end-of-line (BEOL) structures over and in electrical communication with the control logic circuitry, and first isolation material covering the control logic circuitry and the first BEOL structures. A second microelectronic device structure is bonded over the first BEOL structures to form a first assembly. The first assembly is vertically inverted. A third microelectronic device structure comprising a second semiconductor structure is bonded over the vertically inverted first assembly to form a second assembly. Memory cells comprising portions of the second semiconductor structure are formed after forming the second assembly. Second BEOL structures are formed over the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.

Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded. Vias extend through multiple layers of memory cells, including through the support structures and bonding interfaces. Thinning the support structure enables a tighter via pitch, which reduces the portion of the footprint used for vias. The memory cells may include three-dimensional transistors with a recessed gate and extended channel length.

Embodiments of the present disclosure provide power to backend memory of an IC device from the back side of the device. An example IC device with back-side power delivery for backend memory includes a frontend layer with a plurality of frontend components such as frontend transistors, a backend layer (that may include a plurality of layers) with backend memory (e.g., with one or more eDRAM arrays), and a back-side power delivery structure with a plurality of back-side interconnects electrically coupled to the backend memory, where the frontend layer is between the back-side power delivery structure and the backend layer.

An integrated circuit (IC) device includes a lower electrode including a first metal, a dielectric film on the lower electrode, and a conductive interface layer between the lower electrode and the dielectric film. The conductive interface layer includes a metal oxide film including at least one metal element. An upper electrode including a second metal is opposite the lower electrode, with the conductive interface layer and the dielectric film therebetween. To manufacture an IC device, an electrode including a metal is formed adjacent to an insulating pattern on a substrate. A conductive interface layer including a metal oxide film including at least one metal element is selectively formed on a surface of the electrode. A dielectric film is formed to be in contact with the conductive interface layer and the insulating pattern.