Apparatuses and methods for manufacturing semiconductor memory devices are described. An example method includes: forming first interconnects; forming first dielectric layers above the first interconnects in a peripheral region; removing portions of the first dielectric layers to form first openings through the first dielectric layers in the peripheral region to expose the first interconnects at bottoms of the first openings; depositing first conductive material in the peripheral region to form first contact portions in the first openings; forming second dielectric layers on the first dielectric layers and the first contact portions in the peripheral region; removing second portions of the second dielectric layers to form second openings through the second dielectric layers to expose the first contact portions at bottoms of the second openings; depositing second conductive material to form a plurality of second contact portions in the corresponding first openings; and forming second interconnects on the second contact portions.

The present disclosure provides a semiconductor device with a composite dielectric structure and a method for forming the semiconductor device. The semiconductor device includes a conductive contact disposed over a semiconductor substrate, and a first dielectric layer disposed over the conductive contact. A top surface of the conductive contact is exposed by an opening. The semiconductor device also includes a bottom electrode extending along sidewalls of the opening and the top surface of the conductive contact, and a top electrode disposed over the bottom electrode and separated from the bottom electrode by a dielectric structure. The dielectric structure includes a second dielectric layer and dielectric portions disposed over the second dielectric layer. The dielectric portions cover top corners of the opening and extend partially along the sidewalls of the opening.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a capacitor, an electrode, and an interlayer film. The transistor includes a semiconductor layer, a gate, a source, and a drain; the transistor and the capacitor are placed to be embedded in the interlayer film. Below the semiconductor layer, one of the source and the drain is in contact with the electrode. Above the semiconductor layer, the other of the source and the drain is in contact with one electrode of the capacitor.

A battery management circuit, a battery protection circuit, a power storage device, a semiconductor device, a vehicle, and an electronic device, or the like with a novel structure, a low power consumption structure, or a highly integrated structure is provided. The semiconductor device includes a first transistor comprising a first conductor and a first semiconductor over the first conductor, a first insulator over the first transistor, a second conductor provided in an opening of the first insulator, a second transistor over the first insulator, and a third conductor over the second transistor. The first conductor has a function of one of a source electrode and a drain electrode of the first transistor. The first semiconductor and the second conductor overlap each other. The second conductor and the third conductor overlap each other. The third conductor and the second transistor overlap each other. The first semiconductor and the second transistor are electrically connected to each other through the second conductor and the third conductor.

A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. The first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. The semiconductor device also includes a capacitor structure at least partially-disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.

The present disclosure provides a memory circuit, a memory device and an operating method of the memory device. The memory device includes a storage transistor, a variable capacitance device and a control transistor. The variable capacitance device is electrically connected to the gate of the storage transistor, and the control transistor is connected to the storage transistor in series.

A capacitor includes a lower electrode layer including a first conductive layer and a second conductive layer on the first conductive layer, the second conductive layer including SnO.sub.2 doped with an impurity; a dielectric layer on the second conductive layer, the dielectric layer including a rutile-phase oxide; and an upper electrode layer on the dielectric layer.

Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.