Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded. Vias extend through multiple layers of memory cells, including through the support structures and bonding interfaces. Thinning the support structure enables a tighter via pitch, which reduces the portion of the footprint used for vias. The memory cells may include three-dimensional transistors with a recessed gate and extended channel length.

Provided is a step of forming, on a P-layer substrate 20, an N.sup.+ layer 21A to be connected to a source line SL, Si pillars 25a to 25d, N.sup.+ layers 23A to 23D to be connected to bit lines BL1 and BL2, HfO.sub.2 layers 30a and 32 surrounding lower and upper portions of the Si pillars 25a to 25d, a TiN layer 31a to be connected to a plate line PL, and TiN layers 33a and 33b to be connected to word lines WL1 and WL2. P layers 27a to 27d are formed so as to surround the Si pillars 25a to 25d and so as to be deposited on them to form a plurality of dynamic flash memory cells arranged in rows and columns.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line, and the bit line is connected to a sense amplifier circuit via a switch circuit. During a page read operation, page data of a memory cell group selected by the word line is read into a sense amplifier circuit concurrently with a memory cell refresh operation for forming positive hole groups.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line. During a refresh operation, at least one of word lines is selected and a voltage of the channel semiconductor layer of the selected word line is returned to a voltage in a state in which a page is written by controlling voltages applied to the selected word line, the drive control line, the source line, and the bit line and thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer.

A transistor structure including a first doped layer, a second doped layer, a channel layer, a gate, and a dielectric structure is provided. The second doped layer is located on the first doped layer. The channel layer is located between the first doped layer and the second doped layer. The gate penetrates through the second doped layer and the channel layer. The second doped layer and the channel layer respectively surround the gate. The dielectric structure is located between the gate and the second doped layer and located between the gate and the channel layer.

There are an N.sup.+ layer connected to a source line SL and an N.sup.+ layer connected to a bit line BL at both ends of a Si pillar standing on a substrate in a perpendicular direction, a P.sup.+ layer connected to the N.sup.+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connected to a plate line PL, and a second gate conductor layer surrounding a gate HfO.sub.2 layer surrounding the Si pillar and connected to a word line WL. The voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data hold operation of holding a group of holes generated by an impact ionization phenomenon or a gate-induced drain leakage current inside a channel region of the Si pillar and a data erase operation of removing the group of holes from the channel region.

A first impurity layer 101a and a second impurity layer 101b are formed on a substrate Sub at both ends of a Si pillar 100 standing in a vertical direction and having a circular or rectangular horizontal cross-section. Then, a first gate insulating layer 103a and a second gate insulating layer 103b surrounding the Si pillar 100, a first gate conductor layer 104a surrounding the first gate insulating layer 103a, and a second gate conductor layer 104b surrounding the second gate insulating layer 103b are formed. Then, a voltage is applied to the first impurity layer 101a, the second impurity layer 101b, the first gate conductor layer 104a, and the second gate conductor layer 104b to generate an impact ionization phenomenon in a channel region 102 by current flowing between the first impurity layer 101a and the second impurity layer 101b. Of generated electrons and positive holes, the electrons are discharged from the channel region 102 to perform a memory write operation for holding some of the positive holes in the channel region 102, and the positive holes held in the channel region 102 are discharged from one or both of the first impurity layer 101a and the second impurity layer 101b to perform a memory erase operation.

A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of the each of the memory cells is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to one of word lines, and the other is connected to a first driving control line. The first driving control line is provided in common for adjacent ones of the pages, and when in the page erase operation, the memory device applies pulsed voltages to one of the word lines which performs the page erase operation and the first driving control line, and applies a fixed voltage to another one of the word lines which is not selected to perform the page erase operation.