An N.sup.+ layer 11a and N.sup.+ layers 13a to 13d that are disposed on both ends of Si pillars 12a to 12d standing on a substrate 10 in a vertical direction, a TiN layer 18a that surrounds a gate HfO.sub.2 layer 17a surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, a TiN layer 18b that surrounds the gate HfO.sub.2 layer 17a and that extends between the Si pillars 12c and 12d, a TiN layer 26a that surrounds a gate HfO.sub.2 layer 17b surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, and a TiN layer 26b that surrounds the gate HfO.sub.2 layer 17b and that extends between the Si pillars 12c and 12d are formed. Voltages applied to the N.sup.+ layers 11a and 13a to 13d and the TiN layers 18a, 18b, 26a, and 26b are controlled to perform a data write operation of retaining, inside the Si pillars 12a to 12d, a group of positive holes generated by an impact ionization phenomenon and a data erase operation of discharging the group of positive holes from the inside of the Si pillars 12a to 12d.

A semiconductor device according to the embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode opposed to the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided between the gate electrode and the first electrode; and a second insulating layer provided between the gate electrode and the second electrode and having an oxygen atom concentration lower than an oxygen atom concentration of the first insulating layer.

A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that is formed on a substrate and that stands on the substrate in a vertical direction, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first gate conductor layer partially surrounds a side surface of the semiconductor base material, and the second gate conductor layer entirely surrounds the side surface of the semiconductor base material.

A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

On a substrate, dynamic flash memory cell transistors and, on their outside, driving-signal processing circuit transistors are disposed. A source line wiring layer, a bit line wiring layer, a plate line wiring layer, and a word line wiring layer extend in the horizontal direction relative to the substrate and connect, from the outside of a dynamic flash memory region, in the perpendicular direction, to lead-out wiring layers on an insulating layer. The transistors in driving-signal processing circuit regions connect, via multilayered wiring layers, to upper wiring layers on the insulating layer. A high-thermal-conductivity layer is disposed over the entirety of the dynamic flash memory region and in a portion above the bit line wiring layer.

A first semiconductor layer 1 is formed on a substrate, a first impurity layer 3 and a second impurity layer 4 extending in a vertical direction are sequentially disposed on part of the first semiconductor layer 1, their sidewalls and the semiconductor layer 1 are covered by a second gate insulating layer 2, a gate conductor layer 22 and a second insulating layer are disposed in a groove formed there, and a second semiconductor layer 7, n.sup.+ layers 6a and 6c positioned at respective ends of the layer 7 and connected to a source line SL and a bit line BL, respectively, a second gate insulating layer 8 formed to cover the second semiconductor layer 7, and a second gate conductor layer 9 connected to a word line WL are disposed on the second impurity layer. Voltage applied to the source line SL, a plate line PL connected to the first gate conductor layer 22, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes in the channel region 12.

A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate having a first surface and a second surface opposite to each other, and a transistor being arranged on the second surface; forming release holes in the substrate, the release holes extending into the transistors, bottoms of the release holes being located in channel regions of the transistors, and top surfaces of the release holes being flush with the first surface; and forming a conductive structure in the release holes.

In certain aspects, a memory device includes a semiconductor layer, a peripheral circuit including a peripheral transistor in contact with the semiconductor layer, an array of memory cells disposed beside the semiconductor layer and the peripheral circuit, and bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each of the bit lines extends in a second direction perpendicular to the first direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than 2 electron-volts. Some embodiments include a memory array having digit lines extending along a vertical direction and wordlines extending along a horizontal direction. The memory array includes memory cells, with each of the memory cells being uniquely addressed by combination of one of the digit lines and one of the wordlines. Each of the memory cells includes a transistor which has GaP channel material. Each of the transistors has first and second source/drain regions spaced from one another by the GaP channel material. The first source/drain regions are coupled with the digit lines, and each of the memory cells includes a capacitor coupled with the second source/drain region of the associated transistor. Other embodiments are disclosed.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a first array of memory cells. The third semiconductor structure includes a second array of memory cells. Each of the memory cells of the first and second arrays includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The first array of memory cells is coupled to the peripheral circuit across the first bonding interface. The second array of memory cells is coupled to the peripheral circuit across the first bonding interface and the second bonding interfaces.