A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.

Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.

A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. Each DRAM cell unit includes a respective transistor, a respective capacitor and a respective bridge structure. Each bridge structure is configured to electrically couple the respective transistor to the respective capacitor. Each capacitor is elongated in a horizontal direction parallel to the working surface of the substrate.

Provided are a memory cell structure, a memory array structure, a semiconductor structure and a manufacturing method thereof. The memory cell structure includes: a substrate, an active region, a word line structure, an insulating dielectric layer, and a capacitor structure. The substrate has a bit line structure therein, and the active region is positioned on the bit line structure. In a direction perpendicular to the substrate, the active region includes a first connection terminal, a second connection terminal away from the first connection terminal, and a channel region positioned between the first connection terminal and the second connection terminal. In the direction perpendicular to the substrate, the word line structure covers a sidewall of the channel region. The insulating dielectric layer covers an outer side of the word line structure, an outer side of the first connection terminal, and an outer side of the second connection terminal.

A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.

Technologies for fabricating a vertical dynamic random access memory (DRAM) structure include forming a DRAM cell hole through a word line layer and an associated substrate such that a first section of the DRAM cell hole extends through the word line layer and a second section of the DRAM cell hole extends through the substrate in vertical alignment with the first section. A pillar capacitor structure is initially formed using the second section of the DRAM cell hole, followed by the formation of a transistor using the first section of the DRAM cell hole as a channel for the transistor. Due to the use of a common DRAM cell hole, the pillar capacitor structure and the channel are in vertical alignment. The substrate is subsequently flipped and removed from the pillar capacitor structure, which is further processed to form a pillar capacitor. In some embodiments, the channel may be formed from a deposition of indium gallium zinc oxide (IGZO).

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate, a cell capacitor, a channel structure, a lining material, a word line and a bit line. The cell capacitor is disposed over the substrate. The channel structure is disposed over the cell capacitor, wherein the channel structure comprises a horizontal member and at least two vertical members extending from the horizontal member and separated by a ditch on the horizontal member. The lining material surrounds each of the at least two vertical members. The word line encloses the at least two vertical members and partially fills the ditch. The bit line is disposed over the channel structure.

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate having a first top surface. An active region is surrounded by an isolation region in the substrate. A buried power line and a buried signal line are disposed within the substrate and in the active region. A first circuit layer is disposed on the first top surface of the substrate to cover the buried power line and the buried signal line. A second circuit layer is disposed on the first top surface of the substrate and separated from the first circuit layer. A cell capacitor is disposed on and electrically coupled to the first circuit layer.

A semiconductor device is provided. For example, the semiconductor device can include a plurality of transistors that are arranged in an array in an X-Y plane. Each of the transistors can include a channel extending in Z direction. The semiconductor device can further include a plurality of word lines. Each of the word lines can electrically connect neighboring some of the transistors that are arranged in a column in X direction at lateral walls of the channels thereof. The semiconductor device can further include one or more electromagnetic shielding elements. At least one of the electromagnetic shielding elements can be disposed between neighboring two of the transistors that are disposed in a row in Y direction.

A semiconductor device is provided. For example, the semiconductor device can include a plurality of transistors that are arranged in an array in an X-Y plane. Each of the transistors can include a channel extending in Z direction. The semiconductor device can further include a plurality of word lines. Each of the word lines can electrically connect neighboring some of the transistors that are arranged in a column in X direction at lateral walls of the channels thereof. The semiconductor device can further include one or more electromagnetic shielding elements. At least one of the electromagnetic shielding elements can be disposed between neighboring two of the transistors that are disposed in a row in Y direction.