An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

A device, including: a first layer including first transistors and a second layer including second transistors, where at least one of the first transistors is self-aligned to one of the second transistors, where the second transistors are horizontally oriented transistors, and where the second layer includes a plurality of resistive-random-access memory (RRAM) cells, the memory cells including the second transistors.

Some embodiments include memory arrays having rows of fins. Each fin includes a first pedestal, a second pedestal and a trench between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trench between the first and second pedestals. The rows are subdivided amongst deep-type (D) rows and shallow-type (S) rows, with the deep-type rows having deeper channel regions than the shallow-type rows. Some embodiments include rows of fins in which the channel regions along individual rows are subdivided amongst deep-type (D) channel regions and shallow-type (S) channel regions, with the deep-type channel regions being below the shallow-type channel regions.

Some embodiments include a floating body transistor which has a gate structure configured as a bracket having two upwardly-projecting sidewalls joined to a base. A region between the upwardly-projecting sidewalls is an interior region of the bracket. The interior region of the bracket has an interior surface along an upper surface of the base, and along inward surfaces of the upwardly-projecting sidewalls. The sidewalls are a first sidewall and a second sidewall. The first and second sidewalls have first and second notches, respectively, which extend downwardly into the first and second sidewalls. The first and second notches are horizontally aligned with one another. Dielectric material lines the interior surface of the bracket. A semiconductor material body is within the interior region of the bracket and along the dielectric material. The semiconductor material body has a third notch which is horizontally aligned with the first and second notches.

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.

An integrated circuit capacitor array includes a plurality of first electrodes, wherein individual ones of the first electrodes are substantially cylindrical with a base over a substrate and an open top end over the base. A first dielectric material layer spans a distance between the first electrodes but is absent from an interior of the first electrodes, where the first dielectric material layer is substantially planar and bifurcates a height of first electrodes. A second dielectric material layer lines the interior of the first electrodes, and lines portions of an exterior of the first electrodes above and below the first dielectric material layer and a second electrode is within the interior of the first electrodes and is around the exterior of the first electrodes above and below the first dielectric material layer.

A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer and first alignment marks; forming memory control circuits including first single crystal transistors, where the first single crystal transistors include portions of the single crystal layer; forming at least one second level above the first level; performing a first etch step including etching lithography windows within the at least one second level; performing a first lithographic step over the at least one second level aligned to the first alignment marks; and performing additional processing steps to form a plurality of first memory cells within the at last one second level, where each of the plurality of first memory cells include one of a plurality of second transistors, and where the plurality of second transistors are aligned to the first alignment marks with a less than 40 nm alignment error.

Disclosed is a semiconductor memory device comprising a substrate with active patterns including first and second source/drain regions, a gate electrode extending across the active patterns in a first direction between the first and second source/drain regions, a line structure extending across the active patterns in a second direction that is transverse to the first direction and including a bit line electrically connected to the first source/drain region, a device isolation layer within a first trench which defines the active patterns, and contacts coupled to the second source/drain regions. The active pattern includes a first portion extending in a third direction parallel to a top surface of the substrate, and second and third portions connected to opposite ends of the first portion and vertically overlapping respective contacts. The second and third portions extend toward the respective contacts.