A semiconductor chip includes: a memory cell having a bit line, a word line, and a power supply node; a first conductive line formed in a first conductive layer, the bit line including a portion of the first conductive line; a second conductive line formed in a second conductive layer different from the first conductive layer, the word line including a portion of the second conductive line; and a third conductive line formed in a third conductive layer different from the first conductive layer and the second conductive layer, and the power supply node including a portion of the third conductive line; wherein the second conductive line has a thickness which is thicker than those of the first conductive line and the third conductive line, and the first, second and third conductive layers are stacked with one another.

A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

The present disclosure discloses a memory and a manufacturing method thereof. The memory includes: active regions extending in a first direction and word lines extending in a second direction, wherein each of the word lines is partially located between adjacent active regions; the word line includes a gate conductive layer; and, in a direction parallel to the first direction, each of the active regions has an end face facing the word lines, and an extreme difference in distances between the end face and the gate conductive layer is within a preset range.

The present disclosure relates to a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.

A dynamic flash memory cell and a fin transistor are formed on a P layer substrate 10a. The dynamic flash memory cell includes a first insulating layer 11a, a fin P layer 25, N.sup.+ layers 35ba and 35bb, a gate insulating layer 27b, and gate conductor layers 30ba and 30bb; the fin transistor includes a fin P layer 22 including fin P layers 15a and 15b, N.sup.+ layers 35aa and 35ab, a gate insulating layer 27a, and a gate conductor layer 30a; in a perpendicular direction, a top portion of the fin P layer 25 is positioned close to or higher than a top portion of the fin P layer 15a, bottom portions of the gate insulating layers 27a and 27b are positioned close to each other, and a bottom portion of the fin semiconductor layer 15b is positioned within the P layer substrate 10a.

A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step.

To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

Described herein are transistor devices formed using perovskite gate dielectrics. In one example, a transistor includes a high-k perovskite dielectric material between a gate electrode and a thin film semiconductor channel. In another example, four-terminal transistor includes a semiconductor channel, a gate stack that includes a perovskite dielectric layer on one side of the channel, and a body electrode on an opposite side of the channel. The body electrode adjusts a threshold voltage of the transistor.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.