A capacitor structure is provided, which includes a contact layer, an insulating layer, a bottom conductive plate, a dielectric layer and a top conductive plate. The contact layer has first, second, third, fourth and fifth portions arranged from periphery to center. The insulating layer is disposed over the contact layer and has an opening exposing the contact layer. The bottom conductive plate is disposed in the opening and including first, second and third portions extending along a depth direction of the opening and separated from each other and in contact with the first, third and fifth portions of the contact layer, respectively. The dielectric layer is conformally disposed on the bottom conductive plate and in contact with the second and fourth portions of the contact layer. The top conductive plate is disposed on the dielectric layer. A method of manufacturing the capacitor is also provided.

A manufacturing method for memory includes: providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate; removing part of the first isolation layer by a thickness to form discrete first trenches; forming word lines filling the first trenches, wherein the word lines each has a first side wall and a second side wall opposite to each other; forming discrete through holes each being between adjacent word lines; forming a first dielectric layer on surface of exposed first side wall, and forming a second dielectric layer on surface of exposed second side wall; and forming an active layer filling the through holes.

An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

A capacitor that includes a substrate, a dielectric portion, and a conductor layer. The dielectric portion includes a thick film portion and a thin film portion. The thick film portion has a thickness larger than the average thickness of the dielectric portion in a direction perpendicular to the first main surface. The thin film portion has a thickness smaller than the average thickness of the dielectric portion in the direction perpendicular to the first main surface. The thick film portion has a larger relative permittivity than the thin film portion.

An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts. The third interconnections are elongated over the dielectric materials and are configured to provide elongated portions as the upper electrodes of the compensation capacitors. Related methods, memory devices, and electronic systems are disclosed.

A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

A manufacturing method of a semiconductor structure includes: providing a base; forming multiple bit line structures on the base, where the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures; forming a first conductive layer in the trench, where a void is formed in the first conductive layer; removing a part of the first conductive layer to form a first groove, where the bottom of the first groove exposes the void; forming an epitaxial layer on an inner wall of the first groove; and allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void.

A capacitor structure is provided, which includes a contact layer, an insulating layer, a bottom conductive plate, a dielectric layer and a top conductive plate. The contact layer has first, second, third, fourth and fifth portions arranged from periphery to center. The insulating layer is disposed over the contact layer and has an opening exposing the contact layer. The bottom conductive plate is disposed in the opening and including first, second and third portions extending along a depth direction of the opening and separated from each other and in contact with the first, third and fifth portions of the contact layer, respectively. The dielectric layer is conformally disposed on the bottom conductive plate and in contact with the second and fourth portions of the contact layer. The top conductive plate is disposed on the dielectric layer. A method of manufacturing the capacitor is also provided.

Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.