A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.

A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.

A method of manufacturing a capacitor structure includes the following. A first, second, third, fourth, fifth, sixth and seventh portions of a contact layer arrange from periphery to center. A first-conductive layer contacting the first portion forms in an opening. A first-dielectric layer contacting the second portion forms on the first-conductive layer. A second-conductive layer forms on the first-dielectric layer. A second-dielectric layer contacting the third portion forms on the second-conductive layer. A third-conductive layer contacting the fourth portion forms on the second-dielectric layer. A third-dielectric layer contacting the fifth portion forms on the third-conductive layer. A fourth-conductive layer contacting the second-conductive layer forms on the third-dielectric layer. A fourth-dielectric layer contacting the sixth portion forms on the fourth-conductive layer. A fifth-conductive layer contacting the seventh portion forms on the fourth-dielectric layer. A fifth-dielectric layer forms on the fourth-dielectric layer and the fifth-conductive layer.

A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.

A capacitor structure includes a contact layer having first, second, third, fourth and fifth portions arranged from periphery to center, an insulating layer over the contact layer and having an opening exposing the contact layer, a bottom conductive plate in the opening, a dielectric layer conformally on the bottom conductive plate and contacting the second and fourth portions of the contact layer, and a top conductive plate on the dielectric layer. The bottom conductive plate includes first, second and third portions extending along a depth direction of the opening, separated from each other, and contacting the first, third and fifth portions of the contact layer, respectively. The first portion of the bottom conductive plate surrounds the second portion of the bottom conductive plate, and the second portion of the bottom conductive plate surrounds the third portion of the bottom conductive plate.

Aspects of the disclosed invention provide a semiconductor structure for a semiconductor chip with two layers of semiconductor devices, where the first layer of semiconductor devices directly contacts a semiconductor substrate and connects to a first frontside interconnect wiring. The first layer of semiconductor devices includes at least one trench semiconductor device such as a deep trench capacitor. The first frontside interconnect wiring is electrically connected to the second frontside interconnect wiring by one or more joined metal plugs. The second layer of active devices connects to a backside power delivery network and the second frontside interconnect wiring. The semiconductor chip with two layers of semiconductor devices that are bonded together provides one layer of semiconductor devices capable of being in a portion of the semiconductor substrate and a second layer of semiconductor devices with a backside power delivery network.

Provided is a semiconductor memory device including a semiconductor substrate, a plurality of memory active regions each having a long axis and a short axis, and arranged to maintain a first distance between memory active regions along the short axis and maintain a second distance between memory active regions along the long axis, a plurality of logic active regions each including at least a P-channel metal oxide semiconductor transistor and arranged to maintain a third distance therebetween, a first device isolation insulating layer in the first trench with a first portion that corresponds to a region between the memory active regions other along the direction of the long axis including a first nitride insulating layer, and a second device isolation insulating layer in the second trench between the logic active regions and that does not include the first nitride insulating layer, wherein the second distance is substantially the same as the third distance.

The semiconductor structure forming method includes: providing a base, where the base includes a substrate, a plurality of first semiconductor layers and second semiconductor layers; forming a first sidewall and a second sidewall, each including a support layer and an isolation layer formed on a side of the support layer; forming a plurality of recessed portions separated by the first sidewall, the second sidewall, and the second semiconductor layers, where the recessed portions extend in a horizontal direction and are stacked in a vertical direction; forming a first conductive layer and a filling layer in each recessed portion; removing isolation layers located on a side of the first sidewall that is away from the second sidewall and on a side of the second sidewall that is away from the first sidewall; and removing the first conductive layer located at a bottom of each recessed portion.

A semiconductor structure, a method for manufacturing a semiconductor structure, and a memory are provided. The semiconductor structure includes: a plurality of first semiconductor pillars, a plurality of second semiconductor pillars, a first support layer, and a storage structure. The plurality of first semiconductor pillars are arranged in an array in a first direction and in a second direction. Each of the first direction and the second direction is perpendicular to an extending direction of each first semiconductor pillar, and the first direction intersects with the second direction. The first support layer covers sidewalls of top portions of the plurality of first semiconductor pillars. Each second semiconductor pillar is arranged on a respective one of the plurality of first semiconductor pillars. The storage structure is arranged around at least sidewalls of the plurality of first semiconductor pillars and sidewalls of the plurality of second semiconductor pillars.