Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.

Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

A method of manufacturing a memory device includes following steps. A first dielectric layer is formed on the substrate between bit-line structures. First trenches are formed in the first dielectric layer. A second dielectric layer is formed to fill in the first trenches. A portion of the first dielectric layer is removed, so that a top surface of the first dielectric layer is lower than a top surface of the second dielectric layer. A first mask layer is formed to cover the top surfaces of the first and second dielectric layers. A first etching process is performed to form second trenches in the first dielectric layer. A third dielectric layer is formed to fill the second trenches. The first dielectric layer is removed to form contact openings between the second and third dielectric layers. A conductive material is formed to fill in the contact openings.

An integrated circuit device includes: a conductive line structure including a conductive line and an insulating capping pattern; and an insulating spacer including an inner spacer and a first insulating spacer, the inner spacer and the first insulating spacer on a sidewall of the conductive line structure. The first insulating spacer includes: a slit portion; a lower insulating portion spaced apart from the inner spacer such that a separation distance between a portion of the lower insulating portion and the inner spacer decreases with increasing vertical distance from the substrate; and an upper insulating portion contacting the inner spacer. A method of forming the insulating spacer includes: forming a polymer layer on the inner spacer; forming a first insulating spacer layer which contacts each of the inner spacer and the polymer layer; and forming a first insulating spacer by partially removing the first insulating spacer layer.

A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

Semiconductor devices are provided. The semiconductor devices may include an active pattern on a substrate. The active pattern may include a first source/drain region and a second source/drain region. The semiconductor devices may also include a bit line electrically connected to the first source/drain region, a first connection electrode electrically connected to the second source/drain region, and a capacitor on the first connection electrode. The capacitor may include a first electrode, a second electrode, and a dielectric pattern between the first and second electrodes. A lower portion of the dielectric pattern may overlap a top surface of the first connection electrode, and the first electrode may extend on an upper portion of a sidewall of the first connection electrode.

Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.

A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

Some embodiments relate to a memory device including first and second conductive lines extending generally in parallel with one another within over a row of memory cells. A centerline extends generally in parallel with the first and second conductive lines and is spaced between the first and second conductive lines. A first plurality of conductive line segments is over the first conductive line. Conductive line segments of the first plurality of conductive line segments are coupled to different locations on the first conductive line. A second plurality of conductive line segments are disposed over the second conductive line, and are coupled to different locations on the second conductive line.