A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

A fabrication method of three-dimensional programmable memory includes: 1) forming a base structure; 2) trenching the base structure; 3) setting the preset memory structure layer by layer onto the inner wall of strip trench; 4) filling the core medium in the cavity of the strip trench to form core medium layer; 5) setting the isolation trenches and isolation trench holes to isolate the left-right fingers and memory units, respectively, where the isolation trenches encroach at least one memory medium layer at the strip trench, and form a curve by connecting with the strip trenches from end to end. The isolation holes are set at the strip trenches to divide the strip into at least three independent memory bodies and encroach the medium layers of the base structure near the long sides of the strip trenches; and 6) filling the isolation trenches and holes with insulating medium.

A fabrication method of three-dimensional programmable memory includes: 1) forming a base structure; 2) trenching the base structure; 3) setting the preset memory structure layer by layer onto the inner wall of strip trench; 4) filling the core medium in the cavity of the strip trench to form core medium layer; 5) setting the isolation trenches and isolation trench holes to isolate the left-right fingers and memory units, respectively, where the isolation trenches encroach at least one memory medium layer at the strip trench, and form a curve by connecting with the strip trenches from end to end. The isolation holes are set at the strip trenches to divide the strip into at least three independent memory bodies and encroach the medium layers of the base structure near the long sides of the strip trenches; and 6) filling the isolation trenches and holes with insulating medium.

The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.

A method includes forming a first select transistor of a first one-time programmable (OTP) memory bit cell over a substrate, wherein the first select transistor is of a first conductivity type; forming a first anti-fuse transistor of the first OTP memory bit cell over the substrate, wherein the first anti-fuse transistor is of a second conductivity type opposite to the first conductivity type; forming a bit line over the substrate, wherein the bit line is electrically coupled to a source/drain terminal of the first select transistor.

A method includes forming a first select transistor of a first one-time programmable (OTP) memory bit cell over a substrate, wherein the first select transistor is of a first conductivity type; forming a first anti-fuse transistor of the first OTP memory bit cell over the substrate, wherein the first anti-fuse transistor is of a second conductivity type opposite to the first conductivity type; forming a bit line over the substrate, wherein the bit line is electrically coupled to a source/drain terminal of the first select transistor.

A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.

A semiconductor storage device includes first and second memory cells adjacent to each other in the X direction, each of the memory cells having a program transistor and a switch transistor. First and second nanosheets, which are to be channel regions of the program transistors, are exposed from first and second gate interconnects, respectively, at faces on the sides opposed to each other in the X direction. Third and fourth nanosheets, which are to be channel regions of the switch transistors, are exposed from third and fourth gate interconnects, respectively, at faces on the sides opposed to each other in the X direction.

A semiconductor storage device includes first and second memory cells adjacent to each other in the X direction, each of the memory cells having a program transistor and a switch transistor. First and second nanosheets, which are to be channel regions of the program transistors, are exposed from first and second gate interconnects, respectively, at faces on the sides opposed to each other in the X direction. Third and fourth nanosheets, which are to be channel regions of the switch transistors, are exposed from third and fourth gate interconnects, respectively, at faces on the sides opposed to each other in the X direction.