A semiconductor substrate includes a fuse memory that is a write-once memory, a control unit that writes and reads data to and from the fuse memory, and a digital. A wiring layer includes a wiring conductor that connects the digital and an external connection terminal and a plane conductor provided in between the wiring conductor and a surface of the semiconductor substrate. The wiring conductor overlaps the fuse memory when the wiring conductor and the fuse memory are seen in a stacking direction in which the semiconductor substrate and the wiring layer are stacked on top of each other. The plane conductor is arranged in between the wiring conductor and the fuse memory and is connected to a ground potential

A semiconductor substrate includes a fuse memory that is a write-once memory, a control unit that writes and reads data to and from the fuse memory, and a digital. A wiring layer includes a wiring conductor that connects the digital and an external connection terminal and a plane conductor provided in between the wiring conductor and a surface of the semiconductor substrate. The wiring conductor overlaps the fuse memory when the wiring conductor and the fuse memory are seen in a stacking direction in which the semiconductor substrate and the wiring layer are stacked on top of each other. The plane conductor is arranged in between the wiring conductor and the fuse memory and is connected to a ground potential

A probe card for testing or trimming or programming a semiconductor wafer including a first die including a first integrated circuit having a trimmable or programmable component. The probe card including at least one probe arranged to make electrical contact with at least one probe pad arranged on the wafer. The at least one probe pad being electrically connected to the trimmable or programmable component and being arranged in a saw street of the wafer.

A probe card for testing or trimming or programming a semiconductor wafer having a first die including a first integrated circuit having a trimmable or programmable component. The probe card includes at least one probe arranged to make electrical contact with a contact pad of a second die arranged adjacent to the first die. The contact pad of the second die being configured to act as a probe pad and being electrically connected to the trimmable or programmable component of the first die.

The present disclosure provides an anti-fuse type one-time programmable memory cell. The memory cell includes a selection transistor and a gate capacitor, which are connected in series and located in a substrate, the substrate including an active region and an isolation region; in which the gate capacitor includes a gate, a gate oxide layer between the gate and the substrate, and an ion-doped region beneath the gate oxide layer, the ion-doped region being located in the active region in the substrate and overlapping with a part of a lower surface of the gate oxide layer; in which a part of the lower surface of the gate oxide layer that does not overlap with the ion-doped region completely overlaps with the isolation region in the substrate, and the ion-doped region and the isolation region are seamlessly adjacent to each other in the substrate beneath the gate oxide layer.

The present disclosure provides an anti-fuse type one-time programmable memory cell. The memory cell includes a selection transistor and a gate capacitor, which are connected in series and located in a substrate, the substrate including an active region and an isolation region; in which the gate capacitor includes a gate, a gate oxide layer between the gate and the substrate, and an ion-doped region beneath the gate oxide layer, the ion-doped region being located in the active region in the substrate and overlapping with a part of a lower surface of the gate oxide layer; in which a part of the lower surface of the gate oxide layer that does not overlap with the ion-doped region completely overlaps with the isolation region in the substrate, and the ion-doped region and the isolation region are seamlessly adjacent to each other in the substrate beneath the gate oxide layer.

Provided is an anti-fuse structure, an anti-fuse array and a method for forming the same. The anti-fuse structure includes: a substrate; a switching device including a first gate structure, a second gate structure, a first doped region, a second doped region and a third doped region, the first and the second gate structures being arranged on the substrate, the first and the second doped regions being respectively located in the substrate at two sides of the first gate structure, and the second and the third doped regions being respectively located in the substrate at two sides of the second gate structure; and an anti-fuse device including a third gate structure and the third doped region, the second and the third gate structures being respectively located on the substrate at two sides of the third doped region, and the doped regions being configured to form a source or a drain, respectively.

Provided is an anti-fuse structure, an anti-fuse array and a method for forming the same. The anti-fuse structure includes: a substrate; a switching device including a first gate structure, a second gate structure, a first doped region, a second doped region and a third doped region, the first and the second gate structures being arranged on the substrate, the first and the second doped regions being respectively located in the substrate at two sides of the first gate structure, and the second and the third doped regions being respectively located in the substrate at two sides of the second gate structure; and an anti-fuse device including a third gate structure and the third doped region, the second and the third gate structures being respectively located on the substrate at two sides of the third doped region, and the doped regions being configured to form a source or a drain, respectively.

An example one-time programmable (OTP) memory device is provided. The OTP memory device include a passivation layer. A top metal layer is positioned below the passivation layer. The top metal layer includes one or more holes configured to an etching medium to pass through the holes. An array of memory elements is positioned in a memory layer below the top metal layer. A first metal address line layer is positioned below the array of memory elements and includes a plurality of first address lines extending in a first direction. A first end of each memory element being connected to one of the plurality of first metal address lines. A second metal address line layer is positioned below the first metal address line layer and includes a plurality of second metal address lines extending in a second direction. The second direction is different than the first direction.

An example one-time programmable (OTP) memory device is provided. The OTP memory device include a passivation layer. A top metal layer is positioned below the passivation layer. The top metal layer includes one or more holes configured to an etching medium to pass through the holes. An array of memory elements is positioned in a memory layer below the top metal layer. A first metal address line layer is positioned below the array of memory elements and includes a plurality of first address lines extending in a first direction. A first end of each memory element being connected to one of the plurality of first metal address lines. A second metal address line layer is positioned below the first metal address line layer and includes a plurality of second metal address lines extending in a second direction. The second direction is different than the first direction.