An antifuse-type OTP memory cell at least includes a first nanowire, a second nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first gate structure includes a first gate dielectric layer, a second gate dielectric layer and a first gate layer. The first nanowire is surrounded by the first gate dielectric layer. The second nanowire is surrounded by the second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer are surrounded by the first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire and a first terminal of the second nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire. The second drain/source structure is not electrically contacted with a second terminal of the second nanowire.

An antifuse-type OTP memory cell at least includes a first nanowire, a second nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first gate structure includes a first gate dielectric layer, a second gate dielectric layer and a first gate layer. The first nanowire is surrounded by the first gate dielectric layer. The second nanowire is surrounded by the second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer are surrounded by the first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire and a first terminal of the second nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire. The second drain/source structure is not electrically contacted with a second terminal of the second nanowire.

A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.

Provided are a semiconductor chip and a method of manufacturing a semiconductor package including the semiconductor chip. The semiconductor chip includes a front end of line (FEOL) including an active layer, a back end of line (BEOL) including a plurality of metal layers including a wire, an optional dicing line along which dicing is optionally performed, and an isolation block configured to process a signal for a discontinuous wire when the wire is discontinuous by being diced along the optional dicing line, and a chip die on which the active layer is not formed around a cross section cut by the optional dicing line. Thus, the production yield of the semiconductor chip may be improved, and the production costs thereof may be reduced.

Provided are a semiconductor chip and a method of manufacturing a semiconductor package including the semiconductor chip. The semiconductor chip includes a front end of line (FEOL) including an active layer, a back end of line (BEOL) including a plurality of metal layers including a wire, an optional dicing line along which dicing is optionally performed, and an isolation block configured to process a signal for a discontinuous wire when the wire is discontinuous by being diced along the optional dicing line, and a chip die on which the active layer is not formed around a cross section cut by the optional dicing line. Thus, the production yield of the semiconductor chip may be improved, and the production costs thereof may be reduced.

A method of generating an integrated circuit (IC) layout diagram includes overlapping an active region with a plurality of gate regions, thereby defining a program transistor and a read transistor of a one-time-programmable (OTP) bit, overlapping a through via region with a gate region of the plurality of gate regions or with the active region, and overlapping the through via region with a metal region of a back-side metal layer.

The present invention relates to an OTP memory device, a method for operating the OTP memory device and a method for fabricating the OTP memory device. In the OTP memory device, a PN junction is formed between a source-side LDD region and a source region in each OTP memory cell. During programming of the OTP memory cell, the PN junction is broken down, providing one-time programmability. Moreover, its circuit layout is simple, helping to achieve a reduced chip area and lower cost. In the method for fabricating the OTP memory device, OTP memory cells in the OTP memory device and MOS transistors are simultaneously formed on surface regions of a semiconductor substrate, reducing fabrication complexity and cost of the OTP memory device and making it suitable for mass production.

The present invention relates to an OTP memory device, a method for operating the OTP memory device and a method for fabricating the OTP memory device. In the OTP memory device, a PN junction is formed between a source-side LDD region and a source region in each OTP memory cell. During programming of the OTP memory cell, the PN junction is broken down, providing one-time programmability. Moreover, its circuit layout is simple, helping to achieve a reduced chip area and lower cost. In the method for fabricating the OTP memory device, OTP memory cells in the OTP memory device and MOS transistors are simultaneously formed on surface regions of a semiconductor substrate, reducing fabrication complexity and cost of the OTP memory device and making it suitable for mass production.

A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.