According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (ROM) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (ROM) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

A display device in which a plurality of pixels are arranged in an array is provided. Each of the plurality of pixels comprises a current path that includes a light emitting element and a first transistor, and a second transistor for transmitting a luminance signal. The first transistor comprises diffusion regions arranged in the current path, and a gate electrode to which the luminance signal is transmitted from the second transistor. The diffusion regions are of a first conductivity type, and the gate electrode is of a second conductivity type opposite to the first conductivity type.

A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (ROM) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

A semiconductor device includes a fuse transistor in an active region. In a first direction, the active region is defined by first and second element isolation films. The fuse transistor includes a gate dielectric film, a gate electrode, and semiconductor regions on both sides of the gate electrode in a second direction perpendicular to the first direction. In the first direction, the gate dielectric film has a central portion, a first peripheral portion and a second peripheral portion. The central portion is spaced apart from the first element isolation film and the second element isolation film, the first peripheral portion reaches the first element isolation film, and the second peripheral portion reaches the second element isolation film. The central portion of the gate dielectric film has a first thickness, and each of the first peripheral portion and the second peripheral portion has a second thickness greater than the first thickness.

A display device in which a plurality of pixels are arranged in an array is provided. Each of the plurality of pixels comprises a current path that includes a light emitting element and a first transistor, and a second transistor for transmitting a luminance signal. The first transistor comprises diffusion regions arranged in the current path, and a gate electrode to which the luminance signal is transmitted from the second transistor. The diffusion regions are of a first conductivity type, and the gate electrode is of a second conductivity type opposite to the first conductivity type.

A memory device is provided. The memory device includes a substrate and a first stack structure. The first stack structure includes a tunneling layer. The tunneling layer includes Si.sub.xO.sub.yN.sub.z, wherein x:y is 1:0.1 to 1:10, and x:z is 1:0.1 to 1:10. The first stack structure further includes a charge layer disposed over the tunneling layer and a first silicon oxide layer disposed over the charge layer. The first stack structure further includes a first gate line disposed over the first silicon oxide layer. The memory device further includes a source line doped region disposed in the substrate and disposed at the first side of the first stack structure. The memory device further includes a bit line doped region disposed in the substrate and disposed at the second side of the first stack structure. A method for manufacturing the memory device is also provided.

A display device in which a plurality of pixels are arranged in an array is provided. Each of the plurality of pixels comprises a current path that includes a light emitting element and a first transistor, and a second transistor for transmitting a luminance signal. The first transistor comprises diffusion regions arranged in the current path, and a gate electrode to which the luminance signal is transmitted from the second transistor. The diffusion regions are of a first conductivity type, and the gate electrode is of a second conductivity type opposite to the first conductivity type.