In a ROM cell using a vertical nanowire (VNW) FET, the gate of the VNW FET is connected with a word line (WL), the bottom thereof is connected with a bit line (BL), and the top thereof is selectively connected with a ground potential line. The bottom of the VNW FET of the ROM cell is connected to the bit line (BL) irrespective of the data stored in the ROM cell.

A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.

A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate, forming a first bottom source/drain region at sides of a first fin of the plurality of fins in a first transistor region, and forming a second bottom source/drain region at sides of a second fin of the plurality of fins in a second transistor region. The first and second bottom source/drain regions are oppositely doped. In the method, a bottom spacer layer is formed on the first and second bottom source/drain regions, and the bottom spacer layer is removed from the second bottom source/drain region. A high-k dielectric layer is formed on the bottom spacer layer in the first transistor region, and directly formed on the second bottom source/drain region in the second transistor region. The method also includes forming a gate conductor on the high-k dielectric layer.

A method of manufacturing a semiconductor device includes forming a stacked structure, forming an opening in the stacked structure, forming a preliminary channel layer in the opening, forming a channel layer by performing heat treatment on the preliminary channel layer, etching an inner surface of the channel layer, and performing ozone (O.sub.3) treatment on an etched inner surface of the channel layer.

A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate, forming a first bottom source/drain region at sides of a first fin of the plurality of fins in a first transistor region, and forming a second bottom source/drain region at sides of a second fin of the plurality of fins in a second transistor region. The first and second bottom source/drain regions are oppositely doped. In the method, a bottom spacer layer is formed on the first and second bottom source/drain regions, and the bottom spacer layer is removed from the second bottom source/drain region. A high-k dielectric layer is formed on the bottom spacer layer in the first transistor region, and directly formed on the second bottom source/drain region in the second transistor region. The method also includes forming a gate conductor on the high-k dielectric layer.

A non-volatile memory device includes an upper semiconductor layer vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group.

A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.

VFET-based mask-programmable ROM are provided. In one aspect, a method of forming a ROM device includes: forming a bottom drain on a wafer; forming fins on the bottom drain with a top portion having a channel dopant at a different concentration than a bottom portion of the fins; forming bottom/top dummy gates alongside the bottom/top portions of the fins; forming a source in between the bottom/top dummy gates; forming a top drain above the top dummy gates; removing the bottom/top dummy gates; and replacing the bottom/top dummy gates with bottom/top replacement gates, wherein the bottom drain, the bottom replacement gates, the bottom portion of the fins, and the source form bottom VFETs of the ROM device, and wherein the source, the top replacement gates, the top portion of the fins, and the top drain form top VFETs stacked on the bottom VFETs. A ROM device is also provided.

A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.