A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.

Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.

A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.

A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.

A semiconductor device includes an under layer, a stacked body comprising a plurality of conductive layers and insulating layers alternately stacked one over the other in a stacking direction, above the insulating layer, a columnar portion extending into the stacked body in the stacking direction of the stacked body, and a graphene film between at least one of the conductive layers and adjacent insulating layers and between the at least one of the conductive layers and the columnar portion.