A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

A semiconductor device according to an embodiment includes first and second chips, and a first conductor. The first chip includes a first substrate, a first circuit and a first joint metal. The first circuit is provided on the first substrate. The first joint metal is connected to the first circuit. The second chip includes a second substrate, a second circuit, and a second joint metal. The second substrate includes P-type and N-type well regions. The second circuit is provided on the second substrate and includes a first transistor. The second joint metal is connected to the second circuit and the first joint metal. The first conductor is connected to the N-type well region from a top region of the second chip. The P-type well region is arranged between a gate electrode of the first transistor and the N-type well region.

Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

Methods, systems and apparatus for managing capacitors in memory devices, e.g., three-dimensional (3D) memory devices are provided. In one aspect, a capacitor includes: a first terminal, a second terminal conductively insulated from the first terminal, and a capacitance structure that includes a plurality of layers sequentially stacked together. At least one layer includes: one or more first conductive parts and one or more second conductive parts that are conductively insulated in the layer, the one or more first conductive parts being conductively coupled to the first terminal, the one or more second conductive parts being conductively coupled to the second terminal. The at least one layer is configured such that at least one of the one or more second conductive parts forms at least one subordinate capacitor with at least one adjacent first conductive part.

Methods, systems and apparatus for managing capacitors in memory devices, e.g., three-dimensional (3D) memory devices are provided. In one aspect, a capacitor includes: a first terminal, a second terminal conductively insulated from the first terminal, and a capacitance structure that includes a plurality of layers sequentially stacked together. At least one layer includes: one or more first conductive parts and one or more second conductive parts that are conductively insulated in the layer, the one or more first conductive parts being conductively coupled to the first terminal, the one or more second conductive parts being conductively coupled to the second terminal. The at least one layer is configured such that at least one of the one or more second conductive parts forms at least one subordinate capacitor with at least one adjacent first conductive part.

A semiconductor storage device includes a semiconductor substrate including a first region, a second region, and a third region, located apart from each other in such an order in a first direction in an element region. Each of the first to third regions including a source and/or drain region. The semiconductor storage device further includes a first conductor layer provided above the element region and having a first opening; a second conductor layer provided above the element region, having a second opening, and located apart from the first conductor layer in the first direction; a first contact, in the first opening, that is connected to the first region; a second contact, in the second opening, that is connected to the third region; a first memory cell connected to the first contact; and a second memory cell connected to the second contact.

A semiconductor storage device includes a semiconductor substrate including a first region, a second region, and a third region, located apart from each other in such an order in a first direction in an element region. Each of the first to third regions including a source and/or drain region. The semiconductor storage device further includes a first conductor layer provided above the element region and having a first opening; a second conductor layer provided above the element region, having a second opening, and located apart from the first conductor layer in the first direction; a first contact, in the first opening, that is connected to the first region; a second contact, in the second opening, that is connected to the third region; a first memory cell connected to the first contact; and a second memory cell connected to the second contact.