A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending, along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

A microelectronic device comprises a first microelectronic device structure, a second microelectronic device structure vertically neighboring the first microelectronic device structure, and a third microelectronic device structure vertically neighboring the second microelectronic device structure. The first microelectronic device structure comprises a first memory array region and the third microelectronic device structure comprises a second memory array region. The second microelectronic device structure comprises a control logic region comprising a first sub word liner driver region comprising transistor structures in electrical communication with structures of the first microelectronic device structure and a second sub word line driver region comprising additional transistor structures in electrical communication with structures of the third microelectronic device structure. Related microelectronic devices, electronic systems, and methods are also described.

A microelectronic device comprises a first microelectronic device structure, a second microelectronic device structure vertically neighboring the first microelectronic device structure, and a third microelectronic device structure vertically neighboring the second microelectronic device structure. The first microelectronic device structure comprises a first memory array region and the third microelectronic device structure comprises a second memory array region. The second microelectronic device structure comprises a control logic region comprising a first sub word liner driver region comprising transistor structures in electrical communication with structures of the first microelectronic device structure and a second sub word line driver region comprising additional transistor structures in electrical communication with structures of the third microelectronic device structure. Related microelectronic devices, electronic systems, and methods are also described.

A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

A semiconductor device according to an embodiment includes first and second chips, and a first conductor. The first chip includes a first substrate, a first circuit and a first joint metal. The first circuit is provided on the first substrate. The first joint metal is connected to the first circuit. The second chip includes a second substrate, a second circuit, and a second joint metal. The second substrate includes P-type and N-type well regions. The second circuit is provided on the second substrate and includes a first transistor. The second joint metal is connected to the second circuit and the first joint metal. The first conductor is connected to the N-type well region from a top region of the second chip. The P-type well region is arranged between a gate electrode of the first transistor and the N-type well region.

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a single crystalline semiconductor layer, a single crystal epitaxial source semiconductor layer located between the single crystalline semiconductor layer and the alternating stack and epitaxially aligned to the single crystalline semiconductor layer, and a memory stack structure vertically extending through the alternating stack and containing a memory film and an epitaxial vertical semiconductor channel including a single crystal semiconductor material that is epitaxially aligned to the epitaxial source semiconductor layer at an interface.