Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a gate stacked structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked, a vertical structure extending into the gate stacked structure, a floating gate disposed between the vertical structure and the plurality of conductive layers, and a dielectric pattern disposed between the floating gate and the plurality of conductive layers. The floating gate may include a first portion that is adjacent to the vertical structure and a second portion that is adjacent to the dielectric pattern, and the dielectric pattern may contact an upper surface, a lower surface, and a sidewall of the second portion.

Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a gate stacked structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked, a vertical structure extending into the gate stacked structure, a floating gate disposed between the vertical structure and the plurality of conductive layers, and a dielectric pattern disposed between the floating gate and the plurality of conductive layers. The floating gate may include a first portion that is adjacent to the vertical structure and a second portion that is adjacent to the dielectric pattern, and the dielectric pattern may contact an upper surface, a lower surface, and a sidewall of the second portion.

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Provided are a flash memory and a manufacturing method thereof. The flash memory includes a floating gate disposed in a substrate, a first, a second and a third dielectric layers, a source region, a drain region, an erase gate on the second dielectric layer, and a select gate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the exposed surface of the floating gate. The source region is disposed in the substrate at one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate at another side of the floating gate and separated from the first dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

Provided are a flash memory and a manufacturing method thereof. The flash memory includes a floating gate disposed in a substrate, a first, a second and a third dielectric layers, a source region, a drain region, an erase gate on the second dielectric layer, and a select gate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the exposed surface of the floating gate. The source region is disposed in the substrate at one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate at another side of the floating gate and separated from the first dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.