A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure.

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.

A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

A memory device includes an alternating stack of insulating layers, dielectric barrier liners and electrically conductive layers located over a substrate and a memory stack structure extending through each layer in the alternating stack. Each of the dielectric barrier liners is located between vertically neighboring pairs of an insulating layer and an electrically conductive layer within the alternating stack. The memory stack structure includes a memory film and a vertical semiconductor channel, the memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures that are vertically spaced from each other without direct contact between them, and each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion, a silicon oxide blocking dielectric portion, and a dielectric metal oxide blocking dielectric portion.

Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a plurality of barrier structures. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The plurality of barrier structures respectively wrap surfaces of the plurality of gate layers. Each barrier structure includes a first barrier layer and a second barrier layer. The first barrier layer continuously covers a top surface, a bottom surface and a first sidewall of a corresponding gate layer. The second barrier layer covers a second sidewall of the corresponding gate layer opposite to the first sidewall, and connects the first barrier layer. The second barrier layer has a thickness greater than a thickness of the first barrier layer. A method of forming a 3D memory device is also provided.

Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a plurality of barrier structures. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The plurality of barrier structures respectively wrap surfaces of the plurality of gate layers. Each barrier structure includes a first barrier layer and a second barrier layer. The first barrier layer continuously covers a top surface, a bottom surface and a first sidewall of a corresponding gate layer. The second barrier layer covers a second sidewall of the corresponding gate layer opposite to the first sidewall, and connects the first barrier layer. The second barrier layer has a thickness greater than a thickness of the first barrier layer. A method of forming a 3D memory device is also provided.

A semiconductor device includes a substrate having a first region and a second region, a first stack structure in the first region, a first channel structure penetrating through the first stack structure and in contact with the substrate, and a second stack structure on the first stack structure and the first channel structure. The device includes a second channel structure penetrating through the second stack structure and connected to the first channel structure, a first molding structure in the second region, a first alignment structure penetrating through the first molding structure and in contact with the substrate, and a second molding structure on the first molding structure and the first alignment structure. The device includes a second alignment structure penetrating through the second molding structure and connected to the first alignment structure, and a protective layer between the first molding structure and the second molding structure.

A semiconductor device includes a substrate having a first region and a second region, a first stack structure in the first region, a first channel structure penetrating through the first stack structure and in contact with the substrate, and a second stack structure on the first stack structure and the first channel structure. The device includes a second channel structure penetrating through the second stack structure and connected to the first channel structure, a first molding structure in the second region, a first alignment structure penetrating through the first molding structure and in contact with the substrate, and a second molding structure on the first molding structure and the first alignment structure. The device includes a second alignment structure penetrating through the second molding structure and connected to the first alignment structure, and a protective layer between the first molding structure and the second molding structure.

A method for manufacturing a cured product pattern of a curable composition includes the steps of, in sequence, depositing a droplet of the curable composition onto a substrate; bringing a mold having an uneven pattern formed in a surface thereof into contact with the curable composition; curing the curable composition; and releasing a cured product of the curable composition from the mold. The mold has a recess having a bottom surface and a stair structure arranged to form an opening surface that becomes wider from the bottom surface toward the surface of the mold. In the contact step, the curable composition comes into contact with the stair portion after a top of the droplet comes into contact with the bottom surface.