A method of controlling a memory device includes receiving a write instruction; starting a write operation to a first address in response to the write instruction; receiving a first read instruction of the first address; suspending the write operation; and applying a read voltage to a word line corresponding to the first address in a first read operation in response to the first read instruction.

A method of controlling a memory device includes receiving a write instruction; starting a write operation to a first address in response to the write instruction; receiving a first read instruction of the first address; suspending the write operation; and applying a read voltage to a word line corresponding to the first address in a first read operation in response to the first read instruction.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

A non-conformal, highly selective liner for etch methods in semiconductor devices is described. A method comprises forming a film stack on a substrate; etching the film stack to form an opening; depositing a non-conformal liner in the opening; etching the non-conformal liner from the bottom of the opening; and selectively etching the film stack relative to the non-conformal liner to form a logic or memory hole. The non-conformal liner comprises one or more of boron, carbon, or nitrogen.

A non-conformal, highly selective liner for etch methods in semiconductor devices is described. A method comprises forming a film stack on a substrate; etching the film stack to form an opening; depositing a non-conformal liner in the opening; etching the non-conformal liner from the bottom of the opening; and selectively etching the film stack relative to the non-conformal liner to form a logic or memory hole. The non-conformal liner comprises one or more of boron, carbon, or nitrogen.

A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.

A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.

Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.