A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.

A semiconductor device includes: a semiconductor substrate (10) having a first region (NP1) and a second region (NP2); a first insulating layer (2b); a first gate electrode (3b) having a first semiconductor layer (31b) containing an impurity, a first conductive layer (32b) containing titanium, a second conductive layer (33b) containing nitrogen and either titanium or tungsten, and a third conductive layer (34b) containing tungsten; a second insulating layer (4b) provided on the third conductive layer and containing oxygen and silicon; a third insulating layer (5b) provided on the second insulating layer and containing nitrogen and silicon; a first contact (CS) provided on the first region; a second contact (CS) provided on the second region; and a third contact (C0) provided on the third conductive layer of the first gate electrode and penetrating through the second insulating layer and the third insulating layer.

A semiconductor device includes: a semiconductor substrate (10) having a first region (NP1) and a second region (NP2); a first insulating layer (2b); a first gate electrode (3b) having a first semiconductor layer (31b) containing an impurity, a first conductive layer (32b) containing titanium, a second conductive layer (33b) containing nitrogen and either titanium or tungsten, and a third conductive layer (34b) containing tungsten; a second insulating layer (4b) provided on the third conductive layer and containing oxygen and silicon; a third insulating layer (5b) provided on the second insulating layer and containing nitrogen and silicon; a first contact (CS) provided on the first region; a second contact (CS) provided on the second region; and a third contact (C0) provided on the third conductive layer of the first gate electrode and penetrating through the second insulating layer and the third insulating layer.

A semiconductor device includes a first semiconductor structure, and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes a substrate having first and second regions, gate electrodes spaced apart from each other on the first region, extending by different lengths and respectively including a pad region having an upper surface exposed upwardly, interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating through the gate electrodes, gate contact plugs penetrating through the pad region of each of the gate electrodes and extending into the first semiconductor structure, and an insulating structure alternating with the interlayer insulating layers below each of the pad regions and surrounding the gate contact plugs. The insulating structure includes a first insulating layer and a second insulating layer surrounding at least a portion of the first insulating layer and including a material different from any of the first insulating layer.

A semiconductor device includes a first semiconductor structure, and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes a substrate having first and second regions, gate electrodes spaced apart from each other on the first region, extending by different lengths and respectively including a pad region having an upper surface exposed upwardly, interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating through the gate electrodes, gate contact plugs penetrating through the pad region of each of the gate electrodes and extending into the first semiconductor structure, and an insulating structure alternating with the interlayer insulating layers below each of the pad regions and surrounding the gate contact plugs. The insulating structure includes a first insulating layer and a second insulating layer surrounding at least a portion of the first insulating layer and including a material different from any of the first insulating layer.

Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.