In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.

Structures for a memory device and methods of forming a structure for a memory device. The structure includes a first and second source/drain regions in a semiconductor substrate, a first gate stack on the semiconductor substrate, and a second gate stack on the semiconductor substrate adjacent to the first gate stack. The first and second gate stacks are positioned in a lateral direction between the first source/drain region and the second source/drain region. The first gate stack includes first and second gate electrodes, and the first gate electrode includes segments spaced apart along a longitudinal axis of the first gate stack.

Structures for a memory device and methods of forming a structure for a memory device. The structure includes a first and second source/drain regions in a semiconductor substrate, a first gate stack on the semiconductor substrate, and a second gate stack on the semiconductor substrate adjacent to the first gate stack. The first and second gate stacks are positioned in a lateral direction between the first source/drain region and the second source/drain region. The first gate stack includes first and second gate electrodes, and the first gate electrode includes segments spaced apart along a longitudinal axis of the first gate stack.

Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device. The first ferroelectric transistor and the last ferroelectric transistor in the string have a lower threshold voltage than the other ferroelectric transistors.

The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.

In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a gate line structure disposed over the substrate, a gate dielectric layer covering one sidewall surface of the gate line structure and disposed over the substrate, a channel layer disposed to cover the gate dielectric layer and disposed over the substrate, a bit line structure and a resistance change structure to contact different portions of the channel layer over the substrate, and a source line structure disposed in the resistance change structure. The gate line structure includes at least one gate electrode layer pattern and interlayer insulation layer pattern that are alternately stacked along a first direction perpendicular to the substrate, and extends in a second direction perpendicular to the first direction.

A three-dimensional semiconductor memory device is disclosed. The device may include a substrate including a cell array region and a connection region provided at an end portion of the cell array region, an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate, an upper insulating layer provided on the electrode structure, a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes, and first contact plugs provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having a better etch-resistive property than the upper insulating layer.

A semiconductor device includes gate electrodes stacked to be spaced apart from each other on a substrate in a first direction, extending in a second direction, and including pad regions bent in a third direction, sacrificial insulating layers extending from the gate electrodes to be stacked alternately with the interlayer insulating layers, separation regions penetrating through the gate electrodes, extending in the second direction, and spaced apart from each other to be parallel to each other, and a through-wiring region spaced apart from the separation regions to overlap the pad regions between the separation regions adjacent to each other and including contact plugs penetrating through the pad regions. The through-wiring region includes slit regions, and each of the slit regions is disposed to penetrate through the sacrificial insulating layers on one side of a respective pad region.