Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.

A semiconductor device according to an embodiment includes a substrate, first to third conductors, and first and second contacts. The first conductor is provided in a first layer above the substrate. The first contact extends in a first direction, and is provided on the first conductor. The second conductor is provided in the first layer and is insulated from the first conductor. The third conductor is provided between the second conductor and the substrate. The second contact extends in the first direction through the second conductor, and is provided on the third conductor. A width of the second contact, as viewed in a second direction, differs between a portion above a boundary face that is included in the first layer and is parallel to the surface of the substrate, and a portion that is below the boundary face.

In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation. By forming a source region at a position spaced downward from a first upper surface of the fin in a region directly below a memory gate electrode, the current is prevented from flowing concentratedly at the upper end of the fin.

Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

[PROBLEM] An object of the present invention is to provide a nonvolatile memory device having an excellent information retention characteristic, exhibiting high performance, and achieving practical mass-production, and a manufacturing method therefor.

[SOLUTION] A nonvolatile memory device 1 has a laminated structure part including a plurality of Al.sub.2O.sub.3 layers 4 and a plurality of SiO.sub.2 layers 6 formed as two types of insulating layers formed with different compositions and disposed alternately, and an O-M.sub.1-O layer 5 of a 0.5 molecular layer to a 2.0 molecular layer, formed by a chemical bond between a metal element M.sub.1 and oxygen, and disposed on each joining interface between the insulating layers, the metal element M.sub.1 being an element other than elements constituting the insulating layers, and the nonvolatile memory device stores information by modulating an interface dipole induced in the vicinity of the O-M.sub.1-O layer 5 by external electrical stimulation.

[PROBLEM] An object of the present invention is to provide a nonvolatile memory device having an excellent information retention characteristic, exhibiting high performance, and achieving practical mass-production, and a manufacturing method therefor.

[SOLUTION] A nonvolatile memory device 1 has a laminated structure part including a plurality of Al.sub.2O.sub.3 layers 4 and a plurality of SiO.sub.2 layers 6 formed as two types of insulating layers formed with different compositions and disposed alternately, and an O-M.sub.1-O layer 5 of a 0.5 molecular layer to a 2.0 molecular layer, formed by a chemical bond between a metal element M.sub.1 and oxygen, and disposed on each joining interface between the insulating layers, the metal element M.sub.1 being an element other than elements constituting the insulating layers, and the nonvolatile memory device stores information by modulating an interface dipole induced in the vicinity of the O-M.sub.1-O layer 5 by external electrical stimulation.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.