An electronic device comprising a semiconductor memory is provided. The semiconductor memory includes a substrate including a cell region and a peripheral circuit region, the cell region including a first cell region and a second cell region, the first cell region being disposed closer to the peripheral circuit region than the second cell region; second lines disposed over the first lines and extending in a second direction crossing the first direction; memory cells positioned at intersections between the first lines and the second lines in the cell region; a first insulating layer positioned between the first lines, between the second line, or both, in the first cell region; and a second insulating layer positioned between the first lines and between the second lines in the second cell region. A dielectric constant of the first insulating layer is smaller than that of the second insulating layer.

This method comprises the following steps: a) providing a stack successively comprising: a substrate; a first electrode; a first dielectric layer, having a first electrical strength; a second metal electrode; a second dielectric layer, having a second dielectric strength that is strictly less than the first dielectric strength; a third electrode; the first dielectric layer and the second electrode having a first interface, the second dielectric layer and the second electrode having a second interface; b) etching the stack by bombardment with electrically charged species, so as to define resistive memory cells; the bombardment of step b) being adapted so that electrically charged species accumulate at the first and second interfaces of each resistive memory cell, so as to generate an electric field that is strictly less than the first electrical strength and is strictly greater than the second dielectric strength.

The present technology relates to an electronic device and a method of manufacturing the same. The electronic device includes a semiconductor memory. The semiconductor memory includes row lines each extending in a first direction, column lines each extending in a second direction crossing the first direction, memory cells positioned at intersections of the row lines and the column lines, and including first sidewalls facing in the first direction and second sidewalls facing in the second direction, first protective layers respectively formed on the second sidewalls of the memory cells, and second protective layers respectively formed on the first sidewalls of the memory cells. A group of the second protective layers partially surround a sidewall of a corresponding one of the column lines.

A method for fabricating an electronic device including a semiconductor memory includes: forming a memory layer over a substrate; forming a memory element by selectively etching the memory layer, wherein forming the memory element includes forming an etching residue on a sidewall of the memory element, the etching residue including a first metal; and forming a spacer by implanting oxygen and a second metal into the etching residue, the spacer including a compound of the first metal-oxygen-the second metal, the second metal being different from the first metal.

A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.

A semiconductor memory includes first to third lines, the second line crossing the first and third lines between the first line and the third line, a first memory element overlapping an intersection region of the first and second lines between the first line and the second line, the first memory element including a first memory layer, a first electrode under the first memory layer, and a second electrode over the first memory layer, and a second memory element overlapping an intersection region of the second and third lines between the second line and the third line, the second memory element including a second memory layer, a third electrode under the second memory layer, and a fourth electrode over the second memory layer. An electrical resistance relation of the third and fourth electrodes is controlled according to an electrical resistance relation of electrical resistances of the first and second electrodes.

A method of manufacturing a switching element includes forming a first electrode layer over a substrate, forming a switching structure on the first electrode layer, and forming a second electrode layer on the switching structure. The switching structure includes a plurality of unit switching layers that includes a first unit switching layer and a second unit switching layer. Forming the first unit switching layer includes forming a first unit insulation layer, and injecting first dopants into the first unit insulation layer by performing a first ion implantation process. Forming the second unit switching layer includes forming a second unit insulation layer, and injecting second dopants into the second unit insulation layer by performing a second implantation process.

A display apparatus includes a protective layer, a substrate including a non-display area adjacent to a display area, and a sub-pixel in the display area and including a conductive layer, an inorganic insulating layer on the conductive layer, an organic insulating layer on the inorganic insulating layer, and a display device connected to the conductive layer. The display apparatus further includes a power supply line including a first power supply line and a second power supply line electrically connected to the sub-pixel; and an insulating dam as at least one layer in the non-display area. The non-display area includes the insulating dam, the power supply line are placed, and a spaced area which does not include the organic insulating layer. The protective layer covers an exposed portion of the power supply line.

A method of manufacturing a switching element includes forming a pillar-shaped structure over a substrate, performing a dopant injection process to form a first doping region in an insulation layer. The method further includes performing the dopant injection process to form a second doping region in a first electrode, to form a third doping region in a second electrode, or both. The pillar-shaped structure includes the first electrode, the insulation layer, and the second electrode that are disposed over a substrate. The first and second doping regions form a first interface therebetween, and the first and third doping regions form a second interface therebetween. The first doping region corresponds to a region in which a threshold switching operation region is performed.

According to an embodiment, a non-volatile memory device includes a first interconnection, a second interconnection closest to the first interconnection in a first direction, rectifying portions arranged in the first direction between the first interconnection and the second interconnection, and a first resistance change portion arranged between adjacent ones of the rectifying portions in the first direction. Each of the rectifying portions includes a first metal oxide layer and a second metal oxide layer.