H10B63/22

THREE-DIMENSIONAL ARRAY ARCHITECTURE FOR RESISTIVE CHANGE ELEMENT ARRAYS AND METHODS FOR MAKING SAME
20210399219 · 2021-12-23 · ·

A method to fabricate a resistive change element array may include depositing a resistive change material over a substrate and forming a first insulating material over the resistive change material. The method may also include etching a trench in the resistive change material and the first insulating material and forming a cavity in a sidewall of the trench by recessing the resistive change material. The method may further include flowing a conductive material in the cavity and depositing a second insulating material in the trench.

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
20210391387 · 2021-12-16 ·

A semiconductor memory includes a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and a first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein portions of the third line located in the cell region and over the contact plug contact the second line, and part of a remainder of the third line is spaced apart from the second line.

Phase-change memory device having reversed phase-change characteristics and phase-change memory having highly integrated three-dimensional architecture using same
11195996 · 2021-12-07 · ·

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

Switch element and method for manufacturing switch element
11195577 · 2021-12-07 · ·

A switch element includes a first wiring line that is provided in a first insulating film and extends in a first direction; a second wiring line that is provided in a second insulating film and extends in a second direction that intersects the first direction; an ion conductive layer sandwiched between the first wiring line and the second wiring line and directly in contact with the second wiring line in an intersection region where the first wiring line and the second wiring line intersect, and enabled to conduct metal ions supplied from the second wiring line; and a metal oxide film sandwiched between the first wiring line and the ion conductive layer.

Vertical cross-point arrays for ultra-high-density memory applications

An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F.sup.2 may be realized.

MULTI-LAYERED CONDUCTIVE METAL OXIDE STRUCTURES AND METHODS FOR FACILITATING ENHANCED PERFORMANCE CHARACTERISTICS OF TWO-TERMINAL MEMORY CELLS
20220190036 · 2022-06-16 ·

A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

METHOD FOR INCREASING THE SURFACE ROUGHNESS OF A METAL LAYER
20220173163 · 2022-06-02 ·

A method for increasing the surface roughness of a layer based on a metal having a catalytic power, includes fixing fluorine or chlorine on the surface of the metal based layer, by exposing the metal based layer to a plasma formed from a reactive gas containing fluorine or chlorine; exposing the surface of the metal based layer to a humid environment to produce an acid, by reaction of hydrogen from the humid environment with the fluorine or the chlorine fixed on the surface of the metal based layer, the acid reacting with the metal to form residues, the whole of the residues forming a pattern on the surface of the metal based layer, and etching the metal based layer through the residues, so as to transfer the pattern into the metal based layer.

Memory devices and methods of forming the same

Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

Vertical resistive memory device with embedded selectors

A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.

Selector devices for a memory cell

A selector device includes a first electrode composed of a first metal having a first work function. A second electrode is composed of a second metal having a second work function. A selector layer is disposed between the first and second electrodes and is composed of a dielectric material having a conduction band and a valence band defining a band gap of at least 5 electron volts. Dopant atoms are disposed in the selector layer to form a sub-conduction band that is below the conduction band and above the work functions. When a threshold voltage is applied across the first and second electrodes, and a magnitude of the threshold voltage exceeds an energy difference between the sub-conduction band and the work functions, but does not exceed an energy difference between the conduction band and the work functions, an on-current will conduct through the selector layer.