The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device.

Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

Provided is a non-volatile memory including a conductor layer, a memory device, and a selector. The selector is located between and electrically connected to the memory device and the conductive layer. The selector includes a metal filling layer, a barrier layer, and a rectify layer. The metal filling layer is electrically connected to the memory device. The barrier layer is located on the sidewall and the bottom surface of the metal filling layer. The rectify layer is wrapped around the barrier layer. The rectify layer includes a first portion and a second portion. The first portion is located between the barrier layer on the bottom surface of the metal filling layer and the conductive layer. The second portion and the metal filling layer sandwich the barrier layer on the sidewall of the metal filling layer. The first portion has more diffusion paths of metal ions than the second portion.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

A variable resistance semiconductor device includes a lower conductive wiring; a bottom electrode over the lower conductive wiring; a selection element pattern over the bottom electrode; a first intermediate electrode over the selection element pattern; a second intermediate electrode over the first intermediate electrode; a variable resistance element pattern over the second intermediate electrode; a top electrode over the variable resistance element pattern; and an upper conductive wiring over the top electrode. The first intermediate electrode includes a first material. The second intermediate electrode includes a second material which has a better oxidation resistance and a higher work function than the first material.

A semiconductor device with an array of vertically stacked electrochemical random-access memory (ECRAM) devices, includes holes formed in a vertical stack of horizontal electrodes. The horizontal electrodes are horizontally aligned and stacked vertically at different vertical levels within the vertical stack and separated by first fill layers. The semiconductor device includes a stack deposition, including a channel layer, and an electrolyte layer, formed over the vertical stack and holes. Selector layers fill holes. The selector layers include an inner selector layer and outer selector layers. The channel layer, the electrolyte layer and outer selector layers are recessed to the inner selector layer and a fill layer is deposited over the vertical stack. The fill layer has been reduced down to the top of the inner selector layer.

Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a nonvolatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.