A method to fabricate a resistive change element array may include depositing a resistive change material over a substrate and forming a first insulating material over the resistive change material. The method may also include etching a trench in the resistive change material and the first insulating material and forming a cavity in a sidewall of the trench by recessing the resistive change material. The method may further include flowing a conductive material in the cavity and depositing a second insulating material in the trench.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

A semiconductor device including at least one variable resistance device is provided. A variable resistance element includes: an ion supply layer having a top, a bottom and a sidewall connecting the top to the bottom; an ion-receiving layer having an inner sidewall connected to at least a portion of the sidewall of the ion supply layer; a gate pattern connected to an outer sidewall of the ion-receiving layer; and a source pattern connected to one of the top or bottom of the ion supply layer, and a drain pattern connected to the other one or the top or bottom of the ion supply layer. A resistance of the ion supply layer is varies depending on an amount of ions supplied from the ion supply layer to the ion-receiving layer in response to a voltage applied to the gate pattern.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described.

A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.