A semiconductor memory device includes a stack structure comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and positioned between insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and is positioned between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and is positioned between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

A memory device including a first substrate extending in a first direction and a second direction perpendicular to the first direction, the first substrate including a memory cell region and a first peripheral circuit region, and a second substrate, including a second peripheral circuit region, extending in the first and second direction, the second substrate overlapping the first substrate in a third direction perpendicular to the first and second direction. The memory device also including a memory cell array disposed in the memory cell region and including a plurality of vertical channel structures extending in the third direction, a peripheral circuit disposed in the second peripheral circuit region, and a resistor extending in the third direction through the first peripheral circuit region and the second peripheral circuit region. The resistor including a plurality of resistance contact structures overlapping the plurality of vertical channel structures in the first direction.

A resistive RAM module comprises a source electrode and an intermediate electrode that is formed on the source electrode. The intermediate electrode has a closed-curve profile. The resistive RAM module also comprises a memristor element that is deposited on the intermediate electrode. The resistive RAM module also comprises a sink electrode that is in contact with the memristor element. The intermediate electrode is electrically between the source electrode and the memristor element and the memristor element is electrically between the intermediate electrode and the sink electrode.

According to one embodiment, in a nonvolatile semiconductor memory device, in a cell block, a local bit line is connected to a bit line via a select transistor. The local bit line extends in a third direction. A local source line is connected to a source line and extends in the third direction. A plurality of memory cells are connected in parallel between the local source line and the local bit line. Each of the memory cells includes a cell transistor and a resistance change element. The cell transistor has a gate connected to a corresponding one of the word lines and one end connected to one of the local bit line or the local source line. The resistance change element is connected between the other end of the cell transistor and the other one of the local bit line or the local source line.

Embodiments of the present invention include a memory cell that has a vertically-oriented fin. The memory cell may also include a resistive memory device located on a first lateral side of the fin. The resistive memory device may include a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode. The memory cell may also include a vertical field-effect transistor having a metal gate and a gate dielectric contacting a second lateral side of the fin opposite the first lateral side.

Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.

A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.

A semiconductor device includes a stack including alternately stacked conductive films and insulating films, wherein the stack includes an opening penetrating the conductive films and the insulating films, and wherein the stack includes a rounded corner that is exposed to the opening. The semiconductor device also includes a first channel film formed in the opening and including a first curved surface surrounding the rounded corner. The semiconductor device further includes a conductive pad formed in the opening, and a second channel film interposed between the first curved surface of the first channel film and the conductive pad.