A MEMS device includes a bolometer attached to a silicon wafer by a base portion of at least one anchor structure. The base portion comprises a layer stack having a metal-insulator-metal (MIM) configuration such that the base portion acts as a resistive switch such that, when the first DC voltage is applied to the patterned conductive layer, the base portion transitions from a high resistive state to a low resistive state, and, when the second DC voltage is applied to the patterned conductive layer, the base portion transitions from a high resistive state to a low resistive state.

A memory device including a first array of rail structures that extend along a first horizontal direction, in which each of the rail structures are formed to serve as a bottom electrode, and a second array of rail structures that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction. Each of the rail structures in the second array are formed to server as a top electrode. The memory device also includes a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures. The continuous dielectric memory layer providing protection from current leakage between the rail structures of the first array and the rail structures of the second array.

Electrical switching technologies employ the otherwise undesirable line defect in crystalline materials to form conductive filaments. A switching cell includes a crystalline layer disposed between an active electrode and another electrode. The crystalline layer has at least one channel, such as a line defect, extending from one surface of the crystalline layer to the other surface. Upon application of a voltage on the two electrodes, the active electrode provides metal ions that can migrate from the active electrode to the other electrode along the line defect, thereby forming a conductive filament. The switching cell can precisely locate the conductive filament within the line defect and increase the device-to-device switching uniformity.

A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.

A semiconductor structure for a vertical phase change memory cell that includes a bottom electrode on a portion of a semiconductor substrate and a pair of vertical phase change bridge elements that are each on a portion of the bottom electrode. The semiconductor structure for the vertical phase change memory cell includes a dielectric material separating the pair of vertical phase change bridge elements and a top electrode over the pair of vertical phase change bridge elements.

A nanoporous (NP) memory may include a non-porous layer and a nanoporous layer sandwiched between the bottom and top electrodes. The memory may be free of diodes, selectors, and/or transistors that may be necessary in other memories to mitigate crosstalk. The nanoporous material of the nanoporous layer may be a metal oxide, metal chalcogenide, or a combination thereof. Further, the memory may lack any additional components. Further, the memory may be free from requiring an electroformation process to allow switching between ON/OFF states.

An electronic device includes a semiconductor memory that includes: a first conductive pattern disposed over a substrate; a first selection element layer disposed over the first conductive pattern and having one or more first grooves therein, the first grooves overlapping the first conductive pattern; a first variable resistance layer whose sidewalls and bottom are surrounded by the first selection element layer, the first variable resistance layer being buried in the first groove; and a second conductive pattern that overlaps the first variable resistance layer and is disposed over the first variable resistance layer

A method of fabricating a resistive semiconductor memory structure that provides in-situ selective etch of phase change materials during deposition of dielectric at low temperature (in the same chamber). The method provides, to a single processing chamber, a semiconductor wafer including a trimmed resistive memory device structure having one or more layers of phase change material used to form a resistive memory device. The one or more layers of phase change material have oxidized sidewall surfaces as a result of a prior etching step where a whole stack structure of the layers forming the resistive memory structure is etched. Then, an encapsulating of the trimmed resistive memory device structure is performed by depositing, within the processing chamber, using a PECVD, a layer of dielectric material, and during the encapsulating, etching, within the processing chamber, the wafer to selectively remove the phase change material oxidation at the sidewall surfaces.

A variable resistance memory device includes a substrate, a first conductive line on the substrate, the first conductive line extending in a first horizontal direction, a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction, and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell having a selection element layer, an intermediate electrode layer, and a variable resistance layer, and the variable resistance layer having a shape of stairs with a concave center.

An array of memory cells includes a layer of nonpatterned storage material, in accordance with embodiment. In one embodiment, a circuit includes an array of memory cells. The array of memory cells includes first conductive electrodes. The array includes a layer of storage material including a nonpatterned region disposed over the first conductive electrodes. The array includes second conductive electrodes disposed over the nonpatterned region of the storage material. A given memory cell of the array is located where one of the second conductive electrodes overlaps one of the first conductive electrodes across the nonpatterned region of storage material.