Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.

Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

In a semiconductor device, a device structure is positioned over a substrate, where the device structure includes devices. A wiring structure of the semiconductor device is positioned over the substrate and coupled to at least one of the devices. The wiring structure includes at least one of programmable lines and programmable vertical interconnects, where the programmable lines extend along a top surface of the substrate and the programmable vertical interconnects extend along a vertical direction perpendicular to the top surface of the substrate. The programmable lines and the programmable vertical interconnects include a programmable material having a modifiable resistivity in that the programmable lines and the programmable vertical interconnects change between being conductive and being non-conductive in responsive to a current pattern delivered to the programmable lines and the programmable vertical interconnects.

A resistive memory device including a resistive memory pattern; and a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium, wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.

An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.

An in-memory computing architecture is disclosed that can evaluate the transitive closure of graphs using the natural parallel flow of information in 3-D nanoscale crossbars. The architecture can be implemented using 3-D crossbar architectures with as few as two layers of 1-diode 1-resistor (1D1R) interconnects. The architecture avoids memory-processor bottlenecks and can hence scale to large graphs. The approach leads to a runtime complexity of O(n.sup.2) using O(n.sup.2) memristor devices. This compares favorably to conventional algorithms with a time complexity of O((n.sup.3)/p+(n.sup.2) log p) on p processors. The approach takes advantage of the dynamics of 3-D crossbars not available on 2-D crossbars.

Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.

A semiconductor memory device includes a stack structure comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and positioned between insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and is positioned between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and is positioned between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.