The present disclosure discloses a pixel circuit, a display apparatus and a dual-gate driving transistor. The pixel circuit comprises a dual-gate driving transistor having a drain electrically connected to a first power supply terminal; a threshold voltage compensation unit electrically connected to a data terminal, a first control terminal, a first gate of the dual-gate driving transistor, and a source of the dual-gate driving transistor respectively; a mobility compensation unit electrically connected to a sensing signal terminal, a second control terminal, and the source of the dual-gate driving transistor respectively; and a light emitting control unit electrically connected to the data terminal, a third control terminal, a second gate of the dual-gate driving transistor, the source of the dual-gate driving transistor, and a light emitting device respectively. The threshold voltage compensation unit and the mobility compensation unit perform threshold voltage compensation for the dual-gate driving transistor under the control of the data terminal, the first control terminal, the sensing signal terminal, and the second control terminal; and the mobility compensation unit and the light emitting control unit perform mobility compensation for the dual-gate driving transistor and control the dual-gate driving transistor to drive the light emitting device to emit light under the control of the sensing signal terminal, the second control terminal, the data terminal, and the third control terminal.

A driving substrate includes a substrate, a plurality of active devices, a thermal-conducting pattern layer and a buffer layer. The active devices are separately arranged on the substrate. Each active device includes a gate, a channel layer, a gate insulation layer, a source and a drain. The source and the drain expose a portion of the channel layer to define a channel region. The thermal-conducting pattern layer is disposed on the substrate and includes at least one thermal-conducting body and at least one thermal-conducting pattern connected to the thermal-conducting body. The thermal-conducting pattern corresponds to a location of at least one of the channel region, the channel layer, the gate, the source and the drain and each active device. The buffer layer is disposed on the substrate and covers the thermal-conducting pattern layer, and is located between the thermal-conducting pattern and each active device.

An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

An organic thin film transistor includes a transparent base substrate and a transparent gate layer formed on the transparent base substrate. A gate insulating layer includes an oxidized inorganic sub-layer and a non-oxidized organic sub-layer formed on the transparent gate layer. A source electrode and a drain electrode are buried within the non-oxidized organic sub-layer. Each of the source electrode and the drain electrode has a bottom side, and the bottom side surface of each of the source electrode and the drain electrode faces the transparent gate layer and contacts the non-oxidized organic sub-layer. The transparent gate layer is buried within the oxidized inorganic sub-layer, and the oxidized inorganic sub-layer covers a top surface and side surfaces of the transparent gate layer.

A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like.

In accordance with various embodiments of the disclosed subject matter, an organic thin film transistor, and a fabricating method thereof are provided. In some embodiments, the method for forming an organic thin film transistor (OTFT), comprising: forming a transparent gate layer on a transparent base substrate; forming a first initial silicone polymer layer on the transparent gate layer; and performing an oxidization process to partially oxidize the first initial silicone polymer layer to form a gate insulating layer, including an oxidized inorganic sub-layer that contacts the transparent gate layer, and a non-oxidized organic sub-layer.

An electronic component (10) comprising a plurality of switching elements (1) which comprise, in this sequence, a first electrode (16), a molecular layer (18) bonded to a substrate, and a second electrode (20), where the molecular layer essentially consists of molecules (M) which contain a connecting group (V) and an end group (E) having a polar or ionic function, is suitable as memristive device for digital information storage.

A surface modifier for a transparent oxide electrode contains a reactive silyl compound represented by General Formula (1):
RfX-A-SiR.sup.1.sub.3-n(OR.sup.2).sub.n(1)
in which, Rf is an aryl group having 10 or fewer carbon atoms that may have an alkyl substituent having 1 to 5 carbon atoms, wherein at least one hydrogen atom is replaced with a fluorine atom, X represents a divalent group selected from O, NH, C(O)O, C(O)NH, OC(O)NH, NHC(O)NH, or a single bond, A represents a straight chain, branched chain or cyclic aliphatic divalent hydrocarbon group having 1 to 10 carbon atoms, an aromatic divalent hydrocarbon group, or a single bond, a surface-modified transparent oxide electrode formed by coating with the surface modifier. A method for producing a surface-modified transparent oxide electrode is also provided.

A compound represented by Formula (1). [In the formula, X represents a halogen atom or an alkoxy group, R.sup.1 represents any one group selected from an alkyl group having 1 to 5 carbon atoms, a group represented by Formula (R2-1), and a group represented by Formula (R2-2), R.sup.2 represents a group represented by Formula (R2-1) or (R2-2), n0 represents an integer of 0 or greater, n1 represents an integer of 0 to 5, and n2 represents a natural number of 1 to 5.]

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Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.