Patent classifications
H10K10/88
Organic thin film transistor and method of manufacturing organic thin film transistor
Provided are an organic thin film transistor having high bendability and high stability in air and a method of manufacturing the organic thin film transistor. The organic thin film transistor includes: a gas barrier layer consisting of a resin layer and an inorganic layer; a transistor element that is formed on one main surface side of the gas barrier layer and includes a gate electrode, an insulating film, an organic semiconductor layer, a source electrode, and a drain electrode; and a sealing layer that is laminated on a side of the transistor element opposite to the gas barrier layer through an adhesive layer, in which a thickness of the resin layer in the gas barrier layer is less than a thickness ranging from the inorganic layer to the sealing layer in the gas barrier layer.
Organic thin film transistor and method of manufacturing organic thin film transistor
Provided are an organic thin film transistor having high bendability and high stability in air and a method of manufacturing the organic thin film transistor. The organic thin film transistor includes: a gas barrier layer consisting of a resin layer and an inorganic layer; a transistor element that is formed on one main surface side of the gas barrier layer and includes a gate electrode, an insulating film, an organic semiconductor layer, a source electrode, and a drain electrode; and a sealing layer that is laminated on a side of the transistor element opposite to the gas barrier layer through an adhesive layer, in which a thickness of the resin layer in the gas barrier layer is less than a thickness ranging from the inorganic layer to the sealing layer in the gas barrier layer.
Urea (multi)-urethane (meth)acrylate-silane compositions and articles including the same
Compositions of matter described as urea (multi)-urethane (meth)acrylate-silanes having the general formula R.sub.A—NH—C(O)—N(R.sup.4)—R.sup.11—[O—C(O)NH—R.sub.S].sub.n, or R.sub.S—NH—C(O)—N(R.sup.4)—R.sup.11—[O—C(O)NH—R.sub.A].sub.n. Also described are articles including a substrate, a base (co)polymer layer on a major surface of the substrate, an oxide layer on the base (co)polymer layer; and a protective (co)polymer layer on the oxide layer, the protective (co)polymer layer including the reaction product of at least one urea (multi)-urethane (meth)acrylate-silane precursor compound. The substrate may be a (co)polymer film or an electronic device such as an organic light emitting device, electrophoretic light emitting device, liquid crystal display, thin film transistor, or combination thereof. Methods of making such urea (multi)-urethane (meth)acrylate-silane precursor compounds, and their use in composite films and electronic devices are also described. Methods of using multilayer composite films as barrier films in articles selected from solid state lighting devices, display devices, and photovoltaic devices are also described.
Touch panel
A flexible touch panel is provided. Both reduction in thickness and high sensitivity of a touch panel are achieved. The touch panel includes a first flexible substrate, a first insulating layer over the first substrate, a transistor and a light-emitting element over the first insulating layer, a color filter over the light-emitting element, a pair of sensor electrodes over the color filter, a second insulating layer over the sensor electrodes, a second flexible substrate over the second insulating layer, and a protective layer over the second substrate. A first bonding layer is between the light-emitting element and the color filter. The thickness of the first substrate and the second substrate is each 1 μm to 200 μm inclusive. The first bonding layer includes a region with a thickness of 50 nm to 10 μm inclusive.
RINSE - REMOVAL OF INCUBATED NANOTUBES THROUGH SELECTIVE EXFOLIATION
A technology called RINSE (Removal of Incubated Nanotubes through Selective Exfoliation) is demonstrated. RINSE removes carbon nanotube (CNT) aggregates in CNFETs without compromising CNFET performance. In RINSE, CNTs are deposited on a substrate, coated with a thin adhesive layer, and sonicated. The adhesive layer is strong enough to keep the individual CNTs on the substrate, but not the larger CNT aggregates. When combined with a CNFET CMOS process as disclosed here, record CNFET CMOS yield and uniformity can be realized.
Module having a sealing resin layer with radiating member filled depressions
A module with a high degree of design flexibility and excellent radiation characteristics is provided. The module includes a multilayer wiring substrate, mounting components mounted on an upper surface of the multilayer wiring substrate, a sealing resin layer sealing the mounting components, a plurality of depressions in an upper surface of the sealing resin layer, and radiators set in the depressions. The mounting components are components whose amounts of heat generated are smaller than those of the mounting components. A gap between a bottom of each of the depressions arranged in a region overlapping each of the mounting components and the mounting component is shorter than a gap between the bottom of each of the depressions arranged in a region overlapping each of the mounting components and the mounting component as seen from a direction perpendicular to the upper surface of the multilayer wiring substrate.
Touch panel
A flexible touch panel is provided. Both reduction in thickness and high sensitivity of a touch panel are achieved. The touch panel includes a first flexible substrate, a first insulating layer over the first substrate, a transistor and a light-emitting element over the first insulating layer, a color filter over the light-emitting element, a pair of sensor electrodes over the color filter, a second insulating layer over the sensor electrodes, a second flexible substrate over the second insulating layer, and a protective layer over the second substrate. A first bonding layer is between the light-emitting element and the color filter. The thickness of the first substrate and the second substrate is each 1 μm to 200 μm inclusive. The first bonding layer includes a region with a thickness of 50 nm to 10 μm inclusive.
Flexible organic light-emitting display device and method of manufacturing the same
A flexible organic light-emitting display device and a method of manufacturing the same. The flexible organic light-emitting display device includes a metal oxide infiltrated layer as part of at least one of a plurality of organic layers stacked on and around an organic light-emitting device.
LIGHT EMITTING DISPLAY DEVICE INCLUDING HYDROGEN OR OXYGEN ABSORBING LAYER
A light emitting display device includes a lower substrate, a thin film transistor on the lower substrate, a passivation layer disposed on the thin film transistor and including hydrogen, an overcoating layer disposed on the passivation layer and planarizing the passivation layer, a light emitting element disposed on the overcoating layer and including an anode, a light emitting layer on the anode, and a cathode on the light emitting layer, a bank disposed on the overcoating layer and defining a light emitting area, an adhesive layer on the light emitting element and the bank, and a hydrogen absorbing layer disposed on the adhesive layer and including a hydrogen absorbing filler, wherein a side end of the bank is disposed more inwardly than side ends of the adhesive layer and the hydrogen absorbing layer, wherein the side ends of the adhesive layer and the hydrogen absorbing layer are disposed more inwardly than a side end of the overcoating layer.
CMOS Fabrication Methods for Back-Gate Transistor
A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.