A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.

The invention relates to a method for producing a vertical organic field-effect transistor, in which a vertical organic field-effect transistor with a layer arrangement is produced on a substrate, said layer arrangement including transistor electrodes, namely a first electrode (23; 24), a second electrode (23; 24) and a third electrode (32), electrically insulating layers (25; 34) and an organic semiconductor layer (28). In addition, a vertical organic field-effect transistor is provided, which includes a layer arrangement with transistor electrodes on a substrate (21).

An organic light emitting display can include light emitting elements disposed on a substrate; an encapsulation unit disposed on the light emitting elements; touch sensors disposed on the encapsulation unit; first conductive lines connected to the touch sensors; second conductive lines connected to the first conductive lines; and at least one insulating film formed of at least one of an inorganic film or an organic film and disposed between the first and second conductive lines.

A packaging structure and a packaging method are provided. The packaging structure includes a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer, and a carrier top conductive layer inside the carrier dielectric layer and having a top exposed by the carrier dielectric layer. The packaging structure also includes a top semiconductor structure including a top substrate, a first dielectric layer, a zeroth conductive layer, and a second dielectric layer, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer. Further, the packaging structure includes a conductive plug formed on one side of the zeroth conductive layer, and penetrating through the top substrate, the first dielectric layer, and the second dielectric layer, wherein the conductive plug is electrically connected to each of the zeroth conductive layer and the carrier top conductive layer.

A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

A method of manufacturing a display substrate includes: forming a switch unit on a base substrate; forming a planarization layer on one side of the switch unit away from the base substrate, wherein a region, corresponding to an output electrode, of the planarization layer is provided with a planarization layer via hole, and an orthographic projection of the planarization layer via hole onto the base substrate is located within an orthographic projection region of the output electrode onto the base substrate; etching a surface of a region, corresponding to the planarization layer via hole, of the output electrode; and forming a pixel electrode on one side of the planarization layer away from the switch unit, wherein the pixel electrode is in contact with the output electrode through the planarization layer via hole.

A forming method for a silicon-based display panel includes providing a silicon substrate having a display region and a peripheral region surrounding the display region, providing a first set of photomasks corresponding to the display region, using the first set of photo masks in an exposure process of the display region, providing a second set of photomasks corresponding to the peripheral region, and using the second set of photomasks in an exposure process of the peripheral region. The exposure process of the display region and the exposure process of the peripheral region are different process steps. According to the forming method for the silicon-based display panel, splicing of pixel patterns in the display region is not carried out, so that the yield and the display effect are improved.

An array substrate and a method of fabricating the same are described. The array substrate has an active area and a winding area, wherein the array substrate has a base substrate, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, a patterned flat layer, a pixel defining layer, and a support layer. The first metal layer has at least one first wiring pattern. The second metal layer has at least one second wiring pattern. The third metal layer has at least one third wiring pattern. The pixel defining layer together with the support layer within the winding area have at least one undercut structure. The array substrate and the method of fabricating the same can reduce a width of a boundary formed by the winding area.

The present disclosure provides a flexible substrate, the flexible substrate is divided into a display region, a binding region on a side of the display region, a to-be-bent region between the display region and the binding region, two transition regions between the to-be-bent region and the display region and between the to-be-bent region and the binding region respectively; the transition regions comprise a plurality of transition sub-regions arranged in a first direction, the first direction is a direction from the display region to the binding region; the flexible substrate comprises a flexible base and a back film disposed on the flexible base, a portion of the back film is located in the transition regions; in any one of the transition regions, the amount of distribution per unit area of the back film in each of the transition sub-regions gradually decreases in a direction gradually approaching the to-be-bent region.

[Problem] To provide a method for manufacturing an element which does not lead to the occurrence of a short due to etching, and which suppresses the deterioration of a photoelectric conversion layer. [Solution] An element manufacturing method, wherein the method includes the following steps which are performed on an element material including an electrode formed on a substrate, the electrode having a first electrode and a second electrode which are separated from each other, and a photoelectric conversion layer formed in a region that includes the first electrode and the second electrode: a step in which a first back-side electrode and a second back-side electrode are formed at positions on the photoelectric conversion layer corresponding to a first electrode and a second electrode, wherein the first back-side electrode and the second back-side electrode are not connected; a step in which etching is performed using the first back-side electrode and the second back-side electrode as a mask; and a connection electrode formation step in which a connection electrode for connecting the first back-side electrode and the second back-side electrode is formed.