A photoelectric conversion element module (1) includes a plurality of photoelectric conversion elements (15) formed on a light-transmitting base plate (3). The photoelectric conversion elements (15) each include a transparent conductive film (4), a first charge transport layer (5), a power-generating layer (6), and a second charge transport layer (7) stacked in order from a side corresponding to the light-transmitting base plate (3). The second charge transport layer (7) is formed of a porous film that contains a carbon material. Among two of the photoelectric conversion elements (15) that are adjacent to each other, the second charge transport layer (7) of one photoelectric conversion element and the transparent conductive film (4) of the other photoelectric conversion element are electrically connected via a first conductive adhesive layer (9), a current-collecting electrode (11), and a second conductive adhesive layer (14).

A method of making carbon nanotubes is provided, the method includes depositing a catalyst layer on a substrate, placing the substrate having the catalyst layer in a reaction furnace, heating the reaction furnace to a predetermined temperature, introducing a carbon source gas and a protective gas into the reaction furnace to grow a first carbon nanotube segment structure comprising a plurality of metallic carbon nanotube segments, and applying a pulsed electric field to grow a second carbon nanotube segment structure from the plurality of metallic carbon nanotube segments, where the pulsed electric field is a periodic electric field including a plurality of positive electric field pulses and a plurality of negative electric field pulses alternately arranged, and the second carbon nanotube segment structure includes a plurality of semiconducting carbon nanotube segments.

A back-gate carbon nanotube field effect transistor (CNFETs) provides: (1) reduced parasitic capacitance, which decreases the energy-delay product (EDP) thus improving the energy efficiency of digital systems (e.g., very-large-scale integrated circuits) and (2) scaling of transistors to smaller technology nodes (e.g., sub-3 nm nodes). An exemplary back-gate CNFET includes a channel. A source and a drain are disposed on a first side of the channel. A gate is disposed on a second side of the channel opposite to the first side. In this manner, the contacted gate pitch (CGP) of the back-gate CNFET may be scaled down without scaling the physical gate length (L.sub.G) or contact length (L.sub.C). The gate may also overlap with the source and/or the drain in this architecture. In one example, an exemplary CNFET was demonstrated to have a CGP less than 30 nm and 1.6× improvement to EDP compared to top-gate CNFETs.

Quantum dragon materials and devices have unit (total) transmission of electrons for a wide range of electron energies, even though the electrons do not undergo ballistic propagation, when connected optimally to at least two external leads. Quantum dragon materials and devices, as well as those that are nearly quantum dragons, enable embodiments as quantum dragon electronic or optoelectronic devices, including field effect transistors (FETs), sensors, injectors for spin-polarized currents, wires having integral multiples of the conductance quantum, and wires with zero electrical resistance. Methods of devising such quantum dragon materials and devices are also disclosed.

A variable resistance memory device including a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough, a bit line on the stack, a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole, and a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole may be provided. The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.

The present disclosure discloses a device and a method for preparing a high-density aligned carbon nanotube film. The device includes a container main body, a buffer partition plate and a solvent lead-out part. The buffer partition plate is located at a lower part of the container main body. The solvent lead-out part communicates with an interior of the container main body through a through hole in a side wall of the container main body and extends to an outside of the container main body. The method includes injecting a carbon nanotube solution into a container; immersing a substrate in the carbon nanotube solution; injecting a sealing liquid that is immiscible with the carbon nanotube solution along the substrate or the side wall of the container main body; and leading the solvent out or pulling the substrate such that the liquid surface of the substrate undergoes relative motion.

A method for constructing a solar rectenna array by growing carbon nanotube antennas between lines of metal, and subsequently applying a bias voltage on the carbon nanotube antennas to convert the diodes on the tips of the carbon nanotube antennas from metal oxide carbon diodes to geometric diodes. Techniques for preserving the converted diodes by adding additional oxide are also described.

A flex-tolerant structure includes a flexible and foldable substrate and traces on the substrate. Each trace includes a stretch-resistant layer and a metal layer covering the stretch-resistant layer, electrical flow can persist through these layers even if the traces are fractured. A display panel is also disclosed.

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

A method for depositing nanostructures on a substrate comprises: forming a patterned alignment layer on a surface of the substrate, wherein the patterned alignment layer has one or more cavities each having a main region for accommodating at least one template nanostructure therein and a plurality of extension regions extending from the main region and in fluid communication with the main region, and wherein the plurality of extension regions are sized and shaped to not accommodate the at least one template nanostructure; and diffusing template nanostructures into the one or more cavities of the patterned alignment layer.