H10N52/85

Low-Offset Graphene Hall Sensor

A Graphene Hall sensor (GHS) may be provided with a modulated gate bias signal in which the modulated gate bias signal alternates at a modulation frequency between a first voltage that produces a first conductivity state in the GHS and a second voltage that produces approximately a same second conductivity state in the GHS. A bias current may be provided through a first axis of the GHS. A resultant output voltage signal may be provided across a second axis of the Hall sensor that includes a modulated Hall voltage and an offset voltage, in which the Hall voltage is modulated at the modulation frequency. An amplitude of the Hall voltage that does not include the offset voltage may be extracted from the resultant output voltage signal.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
20170040185 · 2017-02-09 ·

A semiconductor device includes a semiconductor element, a substrate formed with a recess in a main surface, a conductive layer formed on the substrate and electrically connected to the semiconductor element, and a sealing resin covering the semiconductor element. The substrate is made of an electrically insulative synthetic resin. The recess has a bottom surface on which the semiconductor element is mounted, and an intermediate surface connected to the main surface and the bottom surface. The bottom surface is orthogonal to the thickness direction of the substrate. The intermediate surface is inclined with respect to the bottom surface.

Controlling a quantum point junction on the surface of an antiferromagnetic topological insulator

Various embodiments include an electrical device comprising an antiferromagnetic topological insulator having a surface comprising a bulk domain wall configured to support a first type of 1D chiral channel, a surface step configured to support a second 1D chiral channel and intersecting the bulk domain wall to form thereat a quantum point junction.

Controlling a quantum point junction on the surface of an antiferromagnetic topological insulator

Various embodiments include an electrical device comprising an antiferromagnetic topological insulator having a surface comprising a bulk domain wall configured to support a first type of 1D chiral channel, a surface step configured to support a second 1D chiral channel and intersecting the bulk domain wall to form thereat a quantum point junction.

MAGNETIC DEVICE AND A METHOD FOR FORMING THE MAGNETIC DEVICE
20250194430 · 2025-06-12 ·

A magnetic device includes a magnetic layer having a ferromagnetic phase to support magnetic skyrmions and an antiferromagnetic phase to annihilate magnetic skyrmions. The magnetic layer transmits between the ferromagnetic and antiferromagnetic phases. A ferroelectric layer is adapted to magnetoelectrically couple with the magnetic layer causing the magnetic layer to transit between the ferromagnetic and antiferromagnetic phases in response to a polarization state of the ferroelectric layer. The polarization state includes a first polarization state corresponding to the ferromagnetic state and a second polarization state corresponding to the antiferromagnetic state. First and second electrodes can be configured to sandwich the magnetic and ferroelectric layers. The first and second electrodes can be adapted to receive applied voltage for switching the polarization state of the ferroelectric layer to control a phase transition of the magnetic layer between the ferromagnetic and antiferromagnetic phases to create or annihilate magnetic skyrmions in the magnetic layer.

MAGNETIC DEVICE AND A METHOD FOR FORMING THE MAGNETIC DEVICE
20250194430 · 2025-06-12 ·

A magnetic device includes a magnetic layer having a ferromagnetic phase to support magnetic skyrmions and an antiferromagnetic phase to annihilate magnetic skyrmions. The magnetic layer transmits between the ferromagnetic and antiferromagnetic phases. A ferroelectric layer is adapted to magnetoelectrically couple with the magnetic layer causing the magnetic layer to transit between the ferromagnetic and antiferromagnetic phases in response to a polarization state of the ferroelectric layer. The polarization state includes a first polarization state corresponding to the ferromagnetic state and a second polarization state corresponding to the antiferromagnetic state. First and second electrodes can be configured to sandwich the magnetic and ferroelectric layers. The first and second electrodes can be adapted to receive applied voltage for switching the polarization state of the ferroelectric layer to control a phase transition of the magnetic layer between the ferromagnetic and antiferromagnetic phases to create or annihilate magnetic skyrmions in the magnetic layer.

MRAM top electrode structure with liner layer

A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

NOVEL SPIN-ORBIT TORQUE MAGNETIC-RAM HAVING SPIN DIFFUSION BARRIER LAYERS
20250322860 · 2025-10-16 ·

A spin Hall effect magnetoresistive memory device comprises a three-terminal magnetoresistive memory cell consisting of an MTJ stack, a spin diffusion barrier layer, a magnetic functional layer with its magnetization either anti-parallel or parallel to the magnetic recording layer magnetization in the MTJ stack, and an SHE-metal layer. Bi-directional recording current along the SHE metal layer directly switches the magnetization of the magnetic functional layer and indirectly switches the magnetization of the magnetic recording layer through the coupling between the magnetic functional layer and the magnetic recording layer.

NOVEL SPIN-ORBIT TORQUE MAGNETIC-RAM HAVING SPIN DIFFUSION BARRIER LAYERS
20250322860 · 2025-10-16 ·

A spin Hall effect magnetoresistive memory device comprises a three-terminal magnetoresistive memory cell consisting of an MTJ stack, a spin diffusion barrier layer, a magnetic functional layer with its magnetization either anti-parallel or parallel to the magnetic recording layer magnetization in the MTJ stack, and an SHE-metal layer. Bi-directional recording current along the SHE metal layer directly switches the magnetization of the magnetic functional layer and indirectly switches the magnetization of the magnetic recording layer through the coupling between the magnetic functional layer and the magnetic recording layer.

Magnetization rotational element, magnetoresistive effect element, and magnetic memory

This magnetization rotational element includes a spin-orbit torque wiring, and a first ferromagnetic layer in contact with the spin-orbit torque wiring, in which the spin-orbit torque wiring includes a first layer, a second layer, and a third layer in order from a side closer to the first ferromagnetic layer, and a coefficient of linear expansion of a material forming the second layer is between a coefficient of linear expansion of a material forming the first layer and a coefficient of linear expansion of a material forming the third layer.