H10N60/0156

Diffusion barriers for metallic superconducting wires
10902978 · 2021-01-26 · ·

In various embodiments, superconducting wires incorporate diffusion barriers composed of Nb alloys or NbTa alloys that resist internal diffusion and provide superior mechanical strength to the wires.

Qubit frequency tuning structures and fabrication methods for flip chip quantum computing devices

A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

DIFFUSION BARRIERS FOR METALLIC SUPERCONDUCTING WIRES
20210020334 · 2021-01-21 ·

In various embodiments, superconducting wires incorporate diffusion barriers composed of Ta alloys that resist internal diffusion and provide superior mechanical strength to the wires.

FABRICATION OF REINFORCED SUPERCONDUCTING WIRES
20200365295 · 2020-11-19 ·

In various embodiments, superconducting wires feature assemblies of clad composite filaments and/or stabilized composite filaments embedded within a wire matrix. The wires may include one or more stabilizing elements for improved mechanical properties.

Superconducting Nanowire Single Photon Detector and Method of Fabrication Thereof

A superconductor device according to some embodiments comprises a superconductor stack, which includes a superconductor layer and a silicon cap layer over the superconductor layer, the cap layer including amorphous silicon. The superconductor device further comprises a metal contact over a portion of the silicon cap layer and electrically-coupled to the superconductor layer. The metal contact comprises a core including a first metal, and an outer layer around the core that includes a second metal. The portion of the silicon cap layer is converted from silicon to a conductive compound including the second metal to provide low-resistance electrical coupling between the superconductor layer and the metal contact. The superconductor device further comprises a waveguide, and the first portion of the cap layer under the metal contact is at a sufficient lateral distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

QUBIT FREQUENCY TUNING STRUCTURES AND FABRICATION METHODS FOR FLIP CHIP QUANTUM COMPUTING DEVICES

A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

SHADOW MASK SIDEWALL TUNNEL JUNCTION FOR QUANTUM COMPUTING
20200321509 · 2020-10-08 ·

A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.

Shadow mask sidewall tunnel junction for quantum computing

A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.

RESONANCE FREQUENCY ADJUSTMENT FOR FIXED-FREQUENCY QUBITS

A method of an embodiment includes forming a capacitor pad for a nonlinear resonator. In an embodiment, the method includes comparing a resonance frequency of the nonlinear resonator to a target frequency to determine whether the resonance frequency falls within a range of the target frequency. A device of an embodiment includes a first capacitor pad comprising a superconducting material, the first capacitor pad configured to couple to a first end of a logic circuit element. In an embodiment, the device includes a second capacitor pad comprising a second superconducting material, the capacitor pad configured to couple to a second end of the logic circuit element. In an embodiment, the second capacitor pad includes a first portion; a second portion; and a bridge configured to electrically connect the first portion and the second portion.

Deposition methodology for superconductor interconnects

A method of forming a superconductor interconnect structure is disclosed. The method includes forming a dielectric layer overlying a substrate, forming an interconnect opening in the dielectric layer, and moving the substrate to a deposition chamber. The method further includes depositing a superconducting metal in the interconnect opening, by performing a series of superconducting deposition and cooling processes to maintain a chamber temperature at or below a predetermined temperature until the superconducting metal has a desired thickness, to form a superconducting element in the superconductor interconnect structure.