H10N60/0241

HIGH-TRANSPARENCY SEMICONDUCTOR-METAL INTERFACES

Techniques that can facilitate high-transparency semiconductor-metal interfaces are provided. In one example, a method can comprise forming a silicon on insulator (SOI) over a wafer. The method can further comprise depositing a metal on the SOI. The method can further comprise forming a structure by dry-etching the metal and dry-etching the SOI. The method can further comprise forming a template over the structure. The method can further comprise etching a portion of the SOI for removal under the metal. The method can further comprise growing a semiconductor where the portion of SOI was removed.

Methods and systems for manufacturing superconductor devices
11719653 · 2023-08-08 · ·

The various embodiments described herein include methods for manufacturing superconductor devices. In some embodiments, a method of manufacturing a superconductor includes: (1) manufacturing a first superconductor device; (2) characterizing the first superconductor device, including: (a) obtaining x-ray diffraction spectra of the first superconductor device; and (b) identifying a ratio of a first cubic phase peak to a second cubic phase peak in the x-ray diffraction spectra; (3) adjusting a manufacturing parameter based on the identified ratio; and (4) manufacturing a second superconductor device with the adjusted manufacturing parameter.

PREPARATION METHOD AND DEVICE OF INDUCTANCE ELEMENT, INDUCTANCE ELEMENT, AND SUPERCONDUCTING CIRCUIT
20210367131 · 2021-11-25 ·

A method and a device for preparing an inductance element, an inductance element, and a superconducting circuit are provided. The method includes acquiring a compound for preparing an inductance element, a superconducting coherence length and a magnetic field penetration depth of the compound meeting a preset condition; and annealing the compound to cause decomposition between a non-superconductor phase and a superconductor phase in the compound to generate the inductance element, the kinetic inductance of the inductance element being greater than the geometric inductance of the inductance element.

METHOD OF MAKING HIGH CRITICAL TEMPERATURE METAL NITRIDE LAYER

A method of fabricating a device including a superconductive layer includes depositing a seed layer on a substrate at a first temperature, the seed layer being a nitride of a first metal, reducing the temperature of the substrate to a second temperature that is lower than the first temperature, increasing the temperature of the substrate to a third temperature that is higher than the first temperature to form a modified seed layer, and depositing a metal nitride superconductive layer directly on the modified seed layer at the third temperature, the superconductive layer being a nitride of a different second metal.

Method of growing titanium nitride on silicon substrate free from silicon nitride interface by using a titanium seed layer

A titanium (Ti) seed layer is formed from a Ti source directly on a surface of a substrate, where the surface is substantially free of oxide and nitride, and a reactive nitrogen species is introduced from a nitrogen plasma source and additional Ti is introduced from the Ti source, wherein the nitrogen plasma: (a) reacts with the Ti seed layer to form TiN and (b) reacts with the additional Ti to form additional TiN. The TiN and additional TiN collectively form a TiN superconducting layer that directly contacts the surface of the substrate.

METHOD OF MAKING HIGH CRITICAL TEMPERATURE METAL NITRIDE LAYER

A method of fabricating a device including a superconductive layer includes depositing a seed layer on a substrate, exposing the seed layer to an oxygen-containing gas or plasma to form a modified seed layer, and after exposing the seed layer to the oxygen-containing gas or plasma depositing a metal nitride superconductive layer directly on the modified seed layer. The seed layer is a nitride of a first metal, and the superconductive layer is a nitride of a different second metal.

High Coherence, Small Footprint Superconducting Qubit Made By Stacking Up Atomically Thin Crystals
20210343923 · 2021-11-04 ·

A superconducting qubit is manufactured by stacking up atomically-thin, crystalline monolayers to form a heterostructure held together by van der Waals forces. Two sheets of superconducting material are separated by a third, thin sheet of dielectric to provide both a parallel plate shunting capacitor and a Josephson tunneling barrier. The superconducting material may be a transition metal dichalcogenide (TMD), such as niobium disilicate, and the dielectric may be hexagonal boron nitride. The qubit is etched, or material otherwise removed, to form a magnetic flux loop for tuning. The heterostructure may be protected by adhering additional layers of the dielectric or other insulator on its top and bottom. For readout, the qubit may be coupled to an external resonator, or the resonator may be integral with one of the sheets of superconducting material.

Method and apparatus for deposition of multilayer device with superconductive film

A physical vapor deposition system includes a chamber, three target supports to targets, a movable shield positioned having an opening therethrough, a workpiece support to hold a workpiece in the chamber, a gas supply to deliver nitrogen gas and an inert gas to the chamber, a power source, and a controller. The controller is configured to move the shield to position the opening adjacent each target in turn, and at each target cause the power source to apply power sufficient to ignite a plasma in the chamber to cause deposition of a buffer layer, a device layer of a first material that is a metal nitride suitable for use as a superconductor at temperatures above 8° K on the buffer layer, and a capping layer, respectively.

Complementary metal-oxide semiconductor compatible patterning of superconducting nanowire single-photon detectors

A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.

COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR COMPATIBLE PATTERNING OF SUPERCONDUCTING NANOWIRE SINGLE-PHOTON DETECTORS

A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.