The present disclosure discloses a device and a method for fabricating a superconducting circuit including a superconducting qubit. The superconducting circuit comprises a bottom electrode interconnecting a superconducting qubit and a first part of the superconducting circuit. The bottom electrode comprises a bottom electrode of the superconducting qubit and a bottom electrode of the first part of the superconducting circuit. The bottom electrode of the superconducting qubit and the bottom electrode of the first part of the superconducting circuit are formed in a first superconducting layer.

The present disclosure discloses a device and a method for fabricating a superconducting circuit including a superconducting qubit. The superconducting circuit comprises a bottom electrode interconnecting a superconducting qubit and a first part of the superconducting circuit. The bottom electrode comprises a bottom electrode of the superconducting qubit and a bottom electrode of the first part of the superconducting circuit. The bottom electrode of the superconducting qubit and the bottom electrode of the first part of the superconducting circuit are formed in a first superconducting layer.

Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include a first superconducting structure and a second superconducting structure disposed on a plane parallel to a silicon wafer surface. A non-superconducting structure may be disposed between the first superconducting structure and the second superconducting structure. A direction of current flow through the non-superconducting structure may be parallel to the silicon wafer surface.

A novel and useful modified semiconductor fabrication technique for realizing reliable semiconductor quantum structures. Quantum structures require a minimization of the parasitic capacitance of the control gate and the quantum well. The modified semiconductor process eliminates the fabrication of the metal, contact, and optionally the raised diffusion layers from the quantum wells, thereby resulting in much lower well and gate capacitances and therefore larger Coulomb blockade voltages. This allows easier implementation of the electronic control circuits in that they can have larger intrinsic noise and relaxed analog resolution. Several processes are disclosed including implementations of semiconductor quantum structures with tunneling through an oxide layer as well as tunneling through a local well depleted region. These techniques can be used in both planar semiconductor processes and 3D, e.g., FinFET, semiconductor processes. A dedicated process masking step is used for realizing the raised diffusions. In addition, the edge of the raised diffusion layer may be placed either in the gate region or the active layer region.

Systems and techniques providing suitable chip structures for facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter can comprise a voltage-controlled oscillator and an antenna. The voltage-controlled oscillator can receive power-on signals from a microcontroller, thereby causing the voltage-controlled oscillator to generate an electromagnetic wave. The antenna can then direct the electromagnetic wave onto a set of one or more capacitor pads of a Josephson junction on a superconducting qubit chip, thereby annealing the Josephson junction. In another example, a voltage regulator and a digital-to-analog converter or digital-to-digital converter can be coupled in series between the microcontroller and the voltage-controlled oscillator, thereby allowing the voltage-controlled oscillator to be voltage and/or frequency tunable and eliminating the need for external power routing as compared to photonic laser annealing. In yet another example, a bipolar-junction and complementary metal-oxide semiconductor stack construction can be employed.

Devices and methods that can facilitate vertical dispersive readout of qubits of a lattice surface code architecture are provided. According to an embodiment, a device can comprise a first substrate that can have a first side and a second side that can be opposite the first side. The first substrate can comprise a read pad that can be located on the first side and a readout resonator that can be located on the second side. The device can further comprise a second substrate that can be connected to the first substrate. The second substrate can comprise a qubit. In some embodiments, the device can further comprise a recess that can be located on the first side of the first substrate. The recess can comprise the read pad.

Methods for initializing a qubit into a pure state, reading the qubit, and arbitrarily rotating the qubit into any quantum state complete in times shorter than the qubit's typical dephasing and relaxation times. These methods provide universal single-qubit control and may be used to implement quantum gates with high fidelity. The methods may be implemented with superconducting qubits, such as heavy fluxonium, and do not rely on a three-dimensional cavity for suppressing spontaneous emission. Therefore, the methods may be implemented using smaller two-dimensional architectures commonly used for superconducting circuits. The methods also work with low-frequency qubits, i.e., qubits for which the energy spacing between the two quantum-computational states is less than the mean thermal energy of a surrounding bath. This reduces the cooling requirements of the qubit while maintaining fidelity.

Disclosed herein is a quantum processor comprising a substrate, a qubit structure formed on the substrate, an electroplated phonon downconversion material, and furrows through the electroplated phonon downconversion material forming a plurality of electroplated phonon downconversion islands coupled to the substrate configured to channel deposited energy away from the qubit structure. Also disclosed are methods of making and using the same.

Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.