A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device.

A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological qubit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.

The method of performing braiding operations can include providing a first Josephson junction including first gates. The method can include providing a second Josephson junction including second gates. The method can include tuning the first gates to dispose a first pair of Majorana fermions a first region. The method can include tuning the second gates to dispose a second pair of Majorana fermions in a second region. The method can include tuning the first gates to dispose a first Majorana fermion in the first region and to dispose a second Majorana fermion in a third region. The method can include tuning the second gates to dispose a third Majorana fermion in a fourth region and to dispose a fourth Majorana fermion in the second region.

In an embodiment, a fabrication method comprises forming first and second electrodes over a substrate that includes a nanowire that extends between, and beneath portions of, the first and second electrodes. The method also includes forming a mask structure that defines at least one opening over a portion of the nanowire and defines at least one overhang portion over a gap between the substrate and the mask. The method further includes depositing a first gate electrode on the substrate and overlapping a third region of the nanowire, and depositing a second gate electrode on the substrate and overlapping a fourth region of the nanowire. The depositing of the first gate electrode includes depositing conductive material through the at least one opening from a first oblique angle, and the depositing of the second gate electrode includes depositing conductive material through the at least one opening from a second oblique angle.

Josephson junctions (JJ) based on bilayers of azimuthally misaligned two-dimensional materials having superconducting states are provided. Also provided are electronic devices and circuits incorporating the JJs as active components and methods of using the electronic devices and circuits. The JJs are formed from bilayers composed of azimuthally misaligned two-dimensional materials having a first superconducting segment and a second superconducting segment separated by a weak-link region that is integrated into the bilayer.

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

The invention is notably directed to a method of operating a superconducting channel. The method relies on a device including: a potentially superconducting material; a gate electrode; and an electrically insulating medium. A channel is defined by the potentially superconducting material. The gate electrode positioned adjacent to the channel, such that an end surface of the gate electrode faces a portion of the channel. The electrically insulating medium is arranged in such a manner that it electrically insulates the gate electrode from the channel. Rendering the channel superconducting by cooling down the device. Next, a voltage difference is applied between the gate electrode and the channel to inject electrons in the channel through the electrically insulating medium and thereby generate a gate current between the gate electrode and the channel. The electrons are injected with an average energy sufficient to modify a critical current I.sub.C of the channel.

A superconductor device includes a substrate. There is a first silicide and a second silicide located on opposite sides of a silicon channel and on top of the substrate. A first superconducting contact is in contact with the first silicide. A second superconducting contact is in contact with the second silicide. A dielectric is located between the first and second superconducting contacts. A gate is on top of the gate dielectric.