A method for improving lifetime and coherence time of a qubit in a quantum mechanical device is provided. The method includes providing a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit having capacitor pads. The method further includes at least one of removing an amount of substrate material from the backside of the substrate at an area opposite the at least one qubit or depositing a superconducting metal layer at the backside of the substrate at the area opposite the at least one qubit to reduce radiofrequency electrical current loss due to at least one of silicon-air (SA) interface, metal-air (MA) interface or silicon-metal (SM) interface so as to enhance a lifetime (T1) and a coherence time (T2) in the at least one qubit.

A Type II superconductor includes a perforated carbonaceous material with an activating material on at least one surface. The activating material a non-polar liquid that does not incorporate Pi-bonding in its structure. The superconductor is manufactured by perforating a carbonaceous material to produce voids and coating at least one surface of the carbonaceous material with the activating material. A superconductive cable includes wires with a perforated carbonaceous material wetted with the activating material on a non-conductive substrate interspersed with non-conducting spacers and surrounded by an insulation layer. The superconductor conducts current at room temperature and above.

A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.

A system includes a plurality of superconducting wires connected in parallel with one another. The plurality of superconducting wires includes a first superconducting wire and a second superconducting wire. The plurality of superconducting wires are configured to, while receiving a bias current provided to the parallel combination of the plurality of superconducting wires, operate in a superconducting state in the absence of a trigger current. The first superconducting wire is configured to, while receiving the bias current, transition to a non-superconducting state in response to receiving the trigger current. The second superconducting wire is configured to, while receiving the bias current, transition to a non-superconducting state in response to the first superconducting wire transitioning to the non-superconducting state.

Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

According to an embodiment of the present invention, a method of producing a computing device includes providing a semiconductor substrate, and patterning a mask on the semiconductor substrate, the mask exposing a first portion of the semiconductor substrate and covering a second portion of the semiconductor substrate. The method includes implanting the first portion of the semiconductor substrate with a dopant. The method includes annealing the first portion of the semiconductor substrate to form an annealed doped region, while maintaining the second portion of the semiconductor substrate as an unannealed portion.

An exemplary tundable capacitor in a quantum system includes a pair of qubits, and a capacitive coupling element coupled between the pair of qubits. The capacitive coupling element includes a plurality of gate terminals. The capacitive coupling element is configured to receive a respective gate voltage at each of the plurality of gate terminals and to adjust a capacitance of the capacitive coupling element in response to the respective gate voltage received at each of the plurality of gate terminals. The capacitance of the capacitive coupling element is configured to control a coupling strength between the pair of qubits.

Superconducting metamaterials composed of lumped-element inductors and capacitors are used to implement microwave photonics with novel dispersion relations and dense mode spectra that can be coupled to qubits. Metamaterial lattices may have qubits coupled to different unit cells in the metamaterial such that each qubit will couple strongly to modes with an antinode at the qubit location. Through simultaneous driving of combinations of modes, large amplitudes are produced at only one or a few unit cells, resulting in large ac Stark shifts of qubits located there, and providing a frequency-addressable qubit array without requiring flux-tunability and with reduced control wiring.

Techniques regarding qubit structures comprising ion implanted Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a strip of superconducting material coupling a first superconducting electrode and a second superconducting electrode. The strip of superconducting material can have a first region comprising an ion implant and a second region that is free from the ion implant.

A qubit device for use in a quantum computing environment includes a semiconductor substrate, an insulating layer disposed on at least a portion of an upper surface of the substrate, and a transition metal silicide (TMSi) heterojunction disposed on at least a portion of an upper surface of the insulating layer. The TMSi heterojunction includes a link layer and at least first and second TMSi regions coupled with the link layer. The link layer may include a normal conductor, thereby forming a superconductor-normal conductor-superconductor (SNS) junction, or a geometric constriction, thereby forming a superconductor-geometric constriction-superconductor (ScS) junction. The link layer may form at least a portion of a channel including intrinsic or doped silicon.