Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.

The present disclosure provides a reaction method with homogeneous-phase supercritical fluid, including: preparing a supercritical fluid and a solute; supplying the supercritical fluid and the solute into a molecular sieve component to uniformly mix the supercritical fluid and the solute in the molecular sieve component, forming a homogeneous-phase supercritical fluid; and supplying the homogeneous-phase supercritical fluid into a reaction chamber for conducting a reaction. The present disclosure further provides an apparatus for homogeneous-phase supercritical fluid reaction, which can be utilized with the reaction method with homogeneous-phase supercritical fluid

Provided are a conductive bridging random access memory (CBRAM) device and a manufacturing method thereof. The CBRAM device includes a first electrode, a semiconductor oxide electrolyte layer formed on the first electrode and including a plurality of metal vacancies, a second electrode formed on the semiconductor oxide electrolyte layer, wherein when a positive voltage is applied to the second electrode, cations are reduced to the metal vacancies in the semiconductor oxide electrolyte layer to form a metal bridge.

A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

System and method to localize a position of an RRAM filament of resistive memory device at very low bias voltages using a scanning laser beam. The approach is non-invasive and allows measurement of a large number of devices for creating statistics relating to the filament formation. A laser microscope system is configured to perform a biasing the RRAM cell with voltage (or current). Concurrent to the applied bias, a laser beam is generated and aimed at different positions of the RRAM cell (e.g., by a raster scanning). Changes in the current (or voltage) flowing through the cell are measured. The method creates a map of the current (or voltage) changes at the different laser positions and detects a spot in the map corresponding to higher (or lower) current (or voltage). The method determines the (x,y) position of the spot compared to the edge/center of the RRAM cell.

The present invention provides a neuromorphic memristor device, which includes a resistive switching layer formed on a lower electrode; and an upper electrode formed on the resistive switching layer, in which the resistive switching layer includes an organic metal halide having a perovskite crystal structure.

To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device includes an active region having resistance properties that can be modified to store one or more data bits in the resistive memory device, and at least one sidewall portion of the active region comprising a dopant configured to suppress conductance paths in the active region proximate to the at least one sidewall portion. The resistive memory device includes terminals configured to couple the active region to associated electrical contacts.

A selector device for a memory cell in a memory array may include a first electrode, and a separator that include a first region of a single-composition layer of a mixed ionic-electronic conduction material with a first concentration of defects; and a second region of a single-composition layer of a transitional metal oxide with a second concentration of defects that is different from the first concentration of defects. The selector device may also include a second electrode, where the separator is between the first electrode and the second electrode.

An electronic device includes a semiconductor memory that includes: a first conductive pattern disposed over a substrate; a first selection element layer disposed over the first conductive pattern and having one or more first grooves therein, the first grooves overlapping the first conductive pattern; a first variable resistance layer whose sidewalls and bottom are surrounded by the first selection element layer, the first variable resistance layer being buried in the first groove; and a second conductive pattern that overlaps the first variable resistance layer and is disposed over the first variable resistance layer

An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.