A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.

A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

An artificial neuron semiconductor device having a three-dimensional structure includes a first electrode to which a clock signal is applied, a second electrode in which an output signal is generated, an insulation column, a plurality of electrode layers for receiving an electrical signal from at least one synapse circuit, and a phase change layer which is divided into at least two parts by the insulation column and is in contact with at least two side surfaces of the insulation column, and the phase change layer is phase-changed by the plurality of electrode layers.

A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.

The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.

Providing a high-density two-terminal memory architecture(s) having performance benefits of two-terminal memory and relatively low fabrication cost, is described herein. By way of example, the two-terminal memory architecture(s) can be constructed on a substrate, in various embodiments, and comprise two-terminal memory cells formed within conductive layer recess structures of the memory architecture. In one embodiment, a conductive layer recess can be created as a horizontal etch in conjunction with a vertical via etch. In another embodiment, the conductive layer recess can be patterned for respective conductive layers of the two-terminal memory architecture.

A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.

There is provided a planar graphene oxide (GO)-based device comprising of multiple resistance state elements in response to an applied voltage and wherein the multiple resistance state elements mimic neural synapse behaviour. The device has multiple application potentials including but not limited to non-volatile electronic memory, sensors, computing for Artificial intelligence (AI) and security. Also disclosed is method of manufacturing a memristor microdevice comprising the steps of patterning metal layer and graphene oxide or reduced graphene oxide thin films on different substrates and producing reduced graphene oxide (rGO) thin film through reduction of the graphene oxide layer. Fabricating thin films of graphene oxide and reduced graphene oxide in the microdevice from an aqueous solution of graphene oxide, results in making the process simple, cost effective, and suitable for mass production of the microdevice.

Some embodiments include an integrated assembly having an insulative mass over a conductive base structure. A conductive interconnect extends through the insulative mass to an upper surface of the conductive base structure. The conductive interconnect includes a conductive liner extending around an outer lateral periphery of the interconnect. The conductive liner includes nitrogen in combination with a first metal. A container-shaped conductive structure is laterally surrounded by the conductive liner. The container-shaped conductive structure includes a second metal. A conductive plug is within the container-shaped conductive structure. Some embodiments include methods of forming conductive interconnects within integrated assemblies.