A cross-bar ReRAM comprising a substrate, a plurality of first columns extending parallel to each other on the top surface of the substrate, wherein each of the plurality of the first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers. A plurality of second columns extending parallel to each other and the plurality of second columns extending perpendicular to the plurality of first columns, wherein the plurality of second columns is located on top of the plurality of first columns, such that the plurality of second columns crosses over the plurality of first columns. A dielectric layer filling in the space between the plurality of first columns and the plurality of second columns, wherein the dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack.

The present invention relates to a non-volatile memory device and a method of fabricating the same. The non-volatile memory device according to an embodiment of the present invention comprises a first electrode; a second electrode; a first oxide layer disposed between the first electrode and the second electrode, and having a reversible filament formed therein; and an oxygen reservoir layer disposed between the first oxide layer and the second electrode, and absorbing oxygens of the first oxide layer to form oxygen vacancy constituting the reversible filament in the first oxide layer. The concentration of the oxygen vacancy may increase from the first oxide layer toward the oxygen reservoir layer.

A semiconductor device includes a substrate, a plurality of word line structures disposed over the substrate to be spaced apart from each other in a first direction perpendicular to a surface of the substrate. Each of the plurality of word line structures extends in a second direction parallel to the surface of the substrate. In addition, the semiconductor device includes a switching layer disposed over the substrate to contact side surfaces of the plurality of word line structures, and bit line structures disposed over the substrate to extend in the first direction and to contact a surface of the switching layer. The switching layer is configured to perform a threshold switching operation, and has a variable programmable threshold voltage.

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

A semiconductor device, includes: a first conductive structure on a substrate; a second conductive structure on the first conductive structure; and a first memory cell structure between the first conductive structure and the second conductive structure, wherein the first memory cell structure includes: a switching material pattern on the first conductive structure; a data storage material pattern on the switching material pattern; and an upper conductive pattern on the data storage material pattern, wherein a first width of a lower region of the data storage material pattern is less than a first width of the switching material pattern, and wherein a first width of the upper conductive pattern is less than a width of an upper region of the data storage material pattern.

An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

A method of manufacturing a semiconductor device comprises: providing a substrate having a base insulation layer; forming, over the base insulation layer, a plurality of first word line structures extending in a first lateral direction and a first switching functional layer disposed between the plurality of first word line structures, the plurality of first word line structures; forming a first interlayer insulation layer on the plurality of first word line structures and the first switching functional layer; forming a plurality of second word line structures and a second switching functional layer disposed between the plurality of second word line structures; performing selective etching to the second switching functional layer, the first interlayer insulation layer, the first switching functional layer, and the base insulation layer to form bit line contact holes; and providing a conductive material in the bit line contact holes to form bit line structures.

A method for fabricating a semiconductor device may include: forming a first line over a substrate; forming a variable resistance layer on the first line; forming a first dielectric layer on the first line and the variable resistance layer; forming a second dielectric layer on the first dielectric layer; removing a portion of the interlayer dielectric layer to expose a portion of the first dielectric layer; and incorporating a dopant into an exposed portion of the first dielectric layer by performing an ion implantation process to convert the portion of the first dielectric layer into a selector layer.

Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode having tapered sides that converge at a top of the first electrode, a dielectric layer disposed on and conforming to the tapered sides of the first electrode, a resistive layer in contact with the top of the first electrode and the dielectric layer, and a second electrode disposed on the resistive layer.