An aspect of the invention relates to an elementary cell that includes a breakdown layer made of dielectric having a thickness that depends on a breakdown voltage, a device and a non-volatile resistive memory mounted in series, the device including an upper selector electrode, a lower selector electrode, a layer made in a first active material, referred to as active selector layer, the device being intended to form a volatile selector; the memory including an upper memory electrode, a lower memory electrode, a layer made in at least one second active material, referred to as active memory layer.

An embodiment of the invention may include a semiconductor structure. The semiconductor structure may include a phase change element located above a heater. The heater may include a conductive element surrounding a dielectric element. The dielectric element may include an air gap.

The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.

A phase-change memory cell includes a heater, a memory region made of a phase-change material located above said heater, and an electrically conductive element positioned adjacent to the memory region and the heater at a first side of the heater. The electrically conductive element extends parallel to a first axis and has, parallel to the first axis, a first dimension at the first side that is greater than a second dimension at a second side opposite to the first side.

Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

A method for making a phase change memory includes a step of forming an array of phase change memory cells, with each cell being separated from neighboring cells in the same line of the array and from neighboring cells in the same column of the array, by the same first distance. The method further includes a step of etching one memory cell out of N, with N being at least equal to 2, in each line or each column.

In certain aspects, a memory device includes a bit line, a plurality of memory cells coupled with the bit line, and N selectors, where N is a positive integer greater than 1, and N word lines. Each one of the plurality of memory cells includes N phase-change memory (PCM) elements. Each one of the N selectors is coupled with a respective one of the N PCM elements. Each one of the N word lines is coupled with a respective one of the N selectors.

A display is described which comprises a plurality of pixels (12), wherein each pixel (12) comprises a plasmonic resonator (26) including first and second metallic material elements (16, 22) and incorporating a layer (18) of a phase change material, the plasmonic resonator (26) being arranged such that in one material state of the phase change material (18) the electric field coupling between the second metallic material element (22) and the phase change material layer (18) is strong and so strong absorption of selected wavelengths of the incident light occurs, whereas in another state of the phase change material (18) the electric field coupling between the metallic material elements (16, 22) and the phase change material layer (18), and between the first and second metallic material elements (16, 22) is weak and so re-radiation of incident light occurs, the pixel (12) being of high reflectance.

A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.