A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.

A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.

A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

Disclosed herein are selector devices and related devices and techniques. For example, in some embodiments, a selector device may include a first electrode, a second electrode, and a selector material stack between the first electrode and the second electrode. The selector material stack may include a dielectric material layer between a first conductive material layer and a second conductive material layer. A first material layer may be present between the first electrode and the first conductive material layer, and a second material layer may be present between the first conductive material layer and the dielectric layer. The first material layer and the second material layer may be diffusion barriers, and the second material layer may be a weaker diffusion barrier than the first material layer.

An ultrathin, carbon-based memristor with a moiré superlattice potential shows prominent ferroelectric resistance switching. The memristor includes a bilayer material, such as Bernal-stacked bilayer graphene, encapsulated between two layers of a layered material, such as hexagonal boron nitride. At least one of the encapsulating layers is rotationally aligned with the bilayer to create the moiré superlattice potential. The memristor exhibits ultrafast and robust resistance switching between multiple resistance states at high temperatures. The memristor, which may be volatile or nonvolatile, may be suitable for neuromorphic computing.

A semiconductor device may include a word line, a bit line crossing the word line, and a memory cell coupled to the word line and the bit line to receive an electrical signal to control the memory cell and including a switching material layer and an oxidation-reduction reversible material layer that is in contact with the switching material layer to allow for either oxidation reaction or reduction reaction to occur in response to different amplitudes and different polarities of the electrical signal, wherein the oxidation-reduction reversible material layer and the switching material layer responds to a first threshold voltage and a first polarity of the electrical signal to generate an oxidation interface between the switching material layer and the oxidation-reduction reversible material layer, and responds to a second threshold voltage and a second polarity of the electrical signal to reduce the generation of the oxidation interface.

A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.

Disclosed herein is an electronic synaptic device comprising: a lower electrode; an upper electrode; and an active layer provided between the lower electrode and the upper electrode and including a plurality of conductive nanoparticles, wherein the conductive nanoparticles are dispersed in a matrix forming a continuous phase, and the matrix is composed of a protein.

The electronic synaptic device according to the present invention has a low switching operation voltage, is capable of implementing a transition phenomenon from a short term potentiation state to a long term potentiation state even with a relatively low voltage, and has high stability; and, therefore, can be preferably applied as a memristive device for implementing neuromorphic computing.

An optical device includes a light-emitting device integrated with a memory device. The memory device include a first electrode and a second electrode, and the light-emitting device includes a third electrode and the second electrode. In such configuration, a first voltage between the second electrode and the third electrode causes the light-emitting device to emit light of a first wavelength, and a second voltage between the first electrode and the second electrode while the memory device is at OFF state causes the light-emitting device to emit light of a second wavelength shorter than the first wavelength or while the memory device is at ON state causes the light-emitting device to emit light of a third wavelength longer than the first wavelength.

A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.